VHDL port type conversion

Discussion in 'VHDL' started by sugobj, Jan 16, 2014.

  1. sugobj

    sugobj

    Joined:
    Dec 16, 2009
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    Is there an easy way to assign the unsigned output of a component to a std_logic_vector? BTW...I'm aware that you can assign it to a std_logic_vector signal then to an unsigned signal. I'm looking for a way to skip the intermediate step.

    For example...

    component Dummy
    port (
    Clk : in std_logic;
    Data : out unsigned(31 downto 0);
    ) ;
    end component;


    signal ChipscopeData : std_logic_vector(31 downto 0);


    InstDummy : Dummy
    port (
    Clk => Clk,
    Data => ChipscopeData <= ERROR Data is unsigned, ChipscopeData is std_logic_vector.
    ) ;
     
    sugobj, Jan 16, 2014
    #1
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