VHDL Help

[deena102]

xc <= x(0);
q(3) <= y(4);
t1 <= (q(3) and xc);
q(2) <= (t1 xor y(3));
t2 <= (q(2) and xc);
q(1) <= (t2 xor y(2));
t3 <= (q(1) and xc);
q(0) <= (t3 xor y(1));
t4 <= (q(0) and xc)
r <= "0000" & (t4 xor y(0));

In this VHDL Code Snippet, I'm getting the error "Cannot read output "q"." while compiling. It is Sequential, each next line needs the previous value. I'm not sure about the Syntax. Please do help...

 

[jeppe]

I believe that q assigned as "out" ?

Try attribute "inout" instead

your welcome
Jeppe

 

[joris]

That, or use an intermediate signal/vector instead of q and only copy it's value into q (that is avoid reading q)

 

[Ukanbal]

what Jeppe says is using a BUFFER (inout) which will allow you to read and write onto. the reason you are getting that error is because you declared 'q' as an OUT and OUT will only let you write onto and wont let you read from

t2 <= (q(2) and xc);
this part of the code for example will require you to read from 'q'

i will suggest you do what Joris says and use a signal for 'q'
example:

Signal temporary : STD_LOGIC_VECTOR (3 DOWNTO 0);

and then inside the code
xc <= x(0);
temporary(3) <= y(4);
t1 <= (temporary(3) and xc);
temporary(2) <= (t1 xor y(3));
t2 <= (temporary(2) and xc);
temporary(1) <= (t2 xor y(2));
t3 <= (temporary(1) and xc);
temporary(0) <= (t3 xor y(1));
t4 <= (temporary(0) and xc)
r <= "0000" & (t4 xor y(0));

q <= temporary;

this should work... but if you dont wanna deal with all that just define 'q' as a BUFFER (or INOUT) and it shouldn't give you the error.