vhdl to verilog - intermediate calculations

Joined
May 12, 2009
Messages
1
Reaction score
0
In VHDL, variables can be used in processes for intermediate calculations. What is the best way to acheive the same thing in Verilog?

for example in VHDL:

process(clk)
variable i : unisnged(7:0);
begin
if rising_edge(clk) then
i := a + b;
x <= i;
y <= i;
end if
end process;

I know one can use regs and blocking assignments in verilog, but this does not seem as clean:

reg [7:0] x,y;
reg [7:0] i;
always @(posedge clk)
begin
i = a + b;
x <= i;
y <= i;
end

The problem I have with this approach is that the reg i is not local to the always block. Also it is declared in exactly the same way as regs x and y, so the intention is less clear.

How are other verilog designers handling intermediate calculations?
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,744
Messages
2,569,482
Members
44,900
Latest member
Nell636132

Latest Threads

Top