In VHDL, variables can be used in processes for intermediate calculations. What is the best way to acheive the same thing in Verilog?
for example in VHDL:
process(clk)
variable i : unisnged(7:0);
begin
if rising_edge(clk) then
i := a + b;
x <= i;
y <= i;
end if
end process;
I know one can use regs and blocking assignments in verilog, but this does not seem as clean:
reg [7:0] x,y;
reg [7:0] i;
always @(posedge clk)
begin
i = a + b;
x <= i;
y <= i;
end
The problem I have with this approach is that the reg i is not local to the always block. Also it is declared in exactly the same way as regs x and y, so the intention is less clear.
How are other verilog designers handling intermediate calculations?
for example in VHDL:
process(clk)
variable i : unisnged(7:0);
begin
if rising_edge(clk) then
i := a + b;
x <= i;
y <= i;
end if
end process;
I know one can use regs and blocking assignments in verilog, but this does not seem as clean:
reg [7:0] x,y;
reg [7:0] i;
always @(posedge clk)
begin
i = a + b;
x <= i;
y <= i;
end
The problem I have with this approach is that the reg i is not local to the always block. Also it is declared in exactly the same way as regs x and y, so the intention is less clear.
How are other verilog designers handling intermediate calculations?