VHDL

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comp.lang.vhdl
S
1200 baud rate generator
  • sagar0205
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0
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978
sagar0205
S
M
12-bit AdderSubtractor VHDL
  • mugz
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2
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7K
mugz
M
A
11bit or 12 bits ?
  • Amit
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5
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1K
David M. Palmer
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10327: can't determine definition of operator ""=""
  • artvandelay
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3
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18K
joris
J
A
10 Reasons Why YOU Should Join Us
  • ammir
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0
Views
919
ammir
A
M
1/2 Convolutional Encoder
  • mits130
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1
Views
1K
Niv
N
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1-element arrays are invalid in VHLD?
  • valentin tihomirov
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1
Views
2K
Mike Treseler
M
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/ and rem, is it synthesizable if the first operand is a power of 2?
  • sonny
Replies
2
Views
1K
Andy
A
D
.txt files as testbench
  • Dek
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2
Views
842
Mike Treseler
M
A
.out file for DLX in VHDL
  • akayrak
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0
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1K
akayrak
A
K
.....Synthesizing signals
  • knight
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0
Views
794
knight
K
U
.. so the mosques were gassed.
  • UnbaisedJustice
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0
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2K
UnbaisedJustice
U
K
-RELAX in ncsim.
  • kk
Replies
3
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2K
Ajeetha
A
A
*URGENT* Anyone keen to helpout to design a Elevator controller VHDLfile using altera *URGENT*
  • asuraseed
Replies
1
Views
1K
alb
A
L
*RANT* Ridiculous EDA software "user license agreements"?
  • license_rant_master
2
Replies
37
Views
3K
marcus.harnisch
M
H
(vhdl-mode) Current context
  • HS
Replies
1
Views
642
Mike Treseler
M
P
(refine question) vhdl and verilog simualtion
  • picnanard
Replies
1
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2K
picnanard
P
M
(newbie) writing a state machine
  • Max
Replies
3
Views
1K
Max
M
M
(newbie) processo or not process?
  • Max
Replies
7
Views
958
J. Bhasker
J
J
(newbie) Configure in vhdl (freehdl)
  • Javier M Mora (jamarier)
Replies
1
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3K
Paul Uiterlinden
P
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(newbie) 2 read/write register
  • Max
Replies
1
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5K
eadgbe
E
F
(8-bit binary to two digit bcd) or (8-bit binary to two digit seven segment)
  • Fangs
Replies
3
Views
12K
darshana
D
M
'X' - Forcing Unknown
  • Matt North
Replies
2
Views
1K
Neo
N
A
'The expression can not be converted to type' error
  • A. Kong
Replies
4
Views
4K
Pieter Hulshoff
P
B
'STD_LOGIC_VECTOR ' to 'unsigned' type casting
  • Ben Nguyen
Replies
6
Views
22K
Niv
N
S
'stable operator
  • sridar
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0
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1K
sridar
S
V
'inout' procedure signal
  • valentin tihomirov
Replies
7
Views
5K
Jonathan Bromley
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'HDL-27 Constant value required' when using signal as index
  • woutput
Replies
1
Views
1K
woutput
W
T
'for' loops in VHDL
  • Thunder
Replies
3
Views
42K
Andy
A
N
'event attribute & modelsim 6.0 problem
  • Nicolas Matringe
Replies
8
Views
1K
Andy
A
P
'driving_value attribute
  • Peter Hermansson
Replies
3
Views
2K
Peter Hermansson
P
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#Error loading design
  • Keltuzad
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0
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2K
Keltuzad
K
C
# ** Warning: /X_FF PULSE WIDTH High VIOLATION ON SET;
  • cheevu
Replies
1
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2K
Jonathan Bromley
J
S
"when" assignments in process ?
  • Sylvain Munaut
Replies
7
Views
1K
Weng Tianxiang
W
W
"when others" question
  • william.mair
Replies
2
Views
950
Peter
P
C
"when others" clause and synthesis
  • Calvin C
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6
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4K
JimLewis
J
M
"Wait on" instead of "Sensitivity List" does not work???
  • Markus Jochim
Replies
3
Views
4K
HT-Lab
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"Value of index is not static"
  • andrezz
Replies
4
Views
2K
andrezz
A
B
"type" can't use for prefix variable
  • benghwee8
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0
Views
666
benghwee8
B
P
"TO_X01" function
  • pankaj.goel
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0
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2K
pankaj.goel
P
N
"Target of signal assignment is not a signal"
  • Nicolas Moreau
Replies
9
Views
9K
Andy
A
A
"sync_fifo" with Almost flags
  • ALuPin
Replies
2
Views
673
ALuPin
A
S
"simple" problem
  • Simone Winkler
Replies
1
Views
813
Jonathan Bromley
J
?
"signal does not hold its value outside clock edge"
  • =?iso-8859-1?q?Guilherme_Corr=EAa?=
Replies
5
Views
9K
=?iso-8859-1?q?Guilherme_Corr=EAa?=
?
J
"Real" Simulations?
  • Jay Davis
Replies
8
Views
1K
Tim Hubberstey
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"read/write synchronization is not available for the selected family"
  • lomtik
Replies
2
Views
2K
lomtik
L
X
"Port 'input' is not constrained" ModelSim error
  • XYZ
Replies
3
Views
6K
XYZ
X
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"Open" banned on procedures - Is this an LRM thing?
  • Tricky
Replies
1
Views
1K
Andy
A
I
"Noughts and Crosses" game in VHDL
  • ibm123
Replies
0
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1K
ibm123
I
A
"NOT" in PORT MAP
  • ALuPin
Replies
3
Views
6K
Andy
A

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