"Port 'input' is not constrained" ModelSim error

Discussion in 'VHDL' started by XYZ, May 8, 2010.

  1. XYZ

    XYZ Guest

    Hello,

    I'm trying to simulate asynchronous dual-rail latch that I wrote. I
    created following test bench (only part of test bench architecture):

    architecture behavior of test_latch is

    component latch is
    port (
    ack_o: in std_logic;
    ack_i: out std_logic;
    input : in dual_rail_vector(2 downto 0);
    output : out dual_rail_vector(2 downto 0)
    );
    end component;

    signal uut_input, uut_output : dual_rail_vector(2 downto 0);
    signal uut_ack_o, uut_ack_i : std_logic;

    begin

    UUT : latch
    port map (
    ack_o => uut_ack_o,
    ack_i => uut_ack_i,
    input => uut_input,
    output => uut_output
    );


    and I get "Port 'input' is not constrained" ModelSim error. In fact,
    latch entity has input and output ports unconstrained, i.e.

    entity latch is
    port (
    ack_o: in std_logic;
    ack_i: out std_logic;
    input : in dual_rail_vector;
    output : out dual_rail_vector
    );
    end;

    When I make an assignment input => uut_input in my test bench (input
    unconstrained, uut_input constrained (2 downto 0) ) doesn't it make the
    input itself constrained? I thought it does.

    How to solve it? Is it necessary to use generic width for all components
    and get rid of unconstrained inputs/outputs?

    Thanks
     
    XYZ, May 8, 2010
    #1
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  2. That's curious. "input" is constrained in any case, because you
    declared it to have the constraint (2 downto 0) on the component.
    Can you show us the declaration of "dual_rail_vector"?
    Also, are you 100% sure the error relates to the
    code you posted, and not to something else? What
    is the exact error message?
     
    Jonathan Bromley, May 8, 2010
    #2
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  3. XYZ

    KJ Guest

    I don't get any error. Works just fine in Modelsim 6.4.
    You're apparently not posting the code that actually has the error.
    See below for code that compiles and simulates just fine. The only
    thing I added to what you had was a package to define your custom type
    'dual_rail_vector' since you didn't have it in your posted code.

    KJ

    ---- Start of code ----
    library ieee;
    use ieee.std_logic_1164.all;
    package pkg_latch is
    alias dual_rail_vector is std_logic_vector;
    end pkg_latch;

    library ieee;
    use ieee.std_logic_1164.all;
    use work.pkg_latch.dual_rail_vector;
    entity latch is
    port (
    ack_o: in std_logic;
    ack_i: out std_logic;
    input : in dual_rail_vector;
    output : out dual_rail_vector
    );
    end;

    architecture rtl of latch is
    begin
    end rtl;

    library ieee;
    use ieee.std_logic_1164.all;
    use work.pkg_latch.dual_rail_vector;

    entity test_latch is
    end test_latch;

    architecture behavior of test_latch is
    component latch is
    port (
    ack_o: in std_logic;
    ack_i: out std_logic;
    input : in dual_rail_vector(2 downto 0);
    output : out dual_rail_vector(2 downto 0)
    );
    end component;

    signal uut_input, uut_output : dual_rail_vector(2 downto 0);
    signal uut_ack_o, uut_ack_i : std_logic;
    begin
    UUT : latch
    port map (
    ack_o => uut_ack_o,
    ack_i => uut_ack_i,
    input => uut_input,
    output => uut_output
    );
    end behavior;
    ---- End of code ----
     
    KJ, May 9, 2010
    #3
  4. XYZ

    XYZ Guest

    Thanks to Jonathan and KJ. After some time I finally figured out what
    was wrong. In Xilinx ISE Project Navigator I didn't select test_latch
    entity but uut instance of latch in test_latch and thus ModelSim
    attempted to simulate the latch entity from latch.vhd and not test_latch
    entity. This obviously resulted in the error I mentioned.

    I have one more question regarding data types. For the moment in my
    package I have defined following:

    type dr is ( 'E', '0', '1', 'X' );
    type dr_vector is array ( natural range <> ) of dr;

    subtype dual_rail is std_ulogic_vector(1 downto 0);
    type dual_rail_vector is array ( natural range <> ) of dual_rail;

    type tab_to_dualrail is array ( dr ) of dual_rail;
    constant to_dualrail : tab_to_dualrail := ( "00", "01", "10", "11" );
    function to_dualrailvector ( arg : dr_vector ) return dual_rail_vector;

    I use dual_rail and dual_rail_vector types in the project because it
    allows me to connect/manipulate both wires separetely. I use dr and
    dr_vector only in test benches to make signal assignment easier, e.g.
    input <= "E0E" which results in input <= ( "00", "01", "00" );
    However, I would like to know whether it would be possible to use dr and
    dr_vector and still be able to access both wires.
     
    XYZ, May 9, 2010
    #4
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