"and" every element of std_logic_vector

[Peter Larsen]

Hi,

I have a std_logic_vector of variable length due to a generic constant. How
do I "and" or "or" every element of this vector with each other?

Thanks in advance

 

[KJ]

Hi,

I have a std_logic_vector of variable length due to a generic constant.
How do I "and" or "or" every element of this vector with each other?

Thanks in advance

Write a function that implements whatever it is you want to do....example to
simply 'or' together all of the even numbered bits in a std_logic_vector is
below

function My_Func(V: std_logic_vector) return std_logic is
variable RetVal: std_logic := '0';
begin
for i in V'range loop
if ((i mod 2) = 0) then
RetVal := RetVal or V(i);
end if;
end loop;
return(RetVal);
end function My_Func;

Then call this function wherever you need it as you would any other
function.

signal y: std_logic;
signal Some_Vector: std_logic_vector(....);
.....
y <= My_Func(Some_Vector)

Kevin Jennings

 

[Eric Smith]

I have a std_logic_vector of variable length due to a generic constant. How
do I "and" or "or" every element of this vector with each other?

v_and <= '1' when some_vector = (some_vector'range => '1') else '0';

v_or <= '1' when some_vector != (some_vector'range => '0') else '0';

 

[kennheinrich]

v_and <= '1' when some_vector = (some_vector'range => '1') else '0';

v_or <= '1' when some_vector != (some_vector'range => '0') else '0';

Applause! Beautiful use of the discrete range aggregate choice. But
this only holds for two-valued logic; if you want to preserve 'X's
you'll need to do an explicit loop, preferably done in a function. But
be careful with the loop example given above; it will only check every
other bit in the vector. You probably want a loop more like the one
below in your function.


variable product : std_logic := '1'; -- use '0' if ORING
....
for i in V'range do
product := product AND V(i);
end loop;
return product;

- Kenn

 

[Mayan Moudgill]

Write a function that implements whatever it is you want to do....example to
simply 'or' together all of the even numbered bits in a std_logic_vector is
below

function My_Func(V: std_logic_vector) return std_logic is
variable RetVal: std_logic := '0';
begin
for i in V'range loop
if ((i mod 2) = 0) then
RetVal := RetVal or V(i);
end if;
end loop;
return(RetVal);
end function My_Func;

Then call this function wherever you need it as you would any other
function.

signal y: std_logic;
signal Some_Vector: std_logic_vector(....);
....
y <= My_Func(Some_Vector)

Kevin Jennings

And how about:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY or_vec IS
PORT(
v : IN std_logic_vector;
vor : OUT std_logic
);
END ENTITY or_vec;

ARCHITECTURE behavior OF or_vec IS
COMPONENT or_vec IS
PORT(
v : IN std_logic_vector;
vor : OUT std_logic
);
END COMPONENT or_vec;
BEGIN
base_case: IF v'length = 1 GENERATE
BEGIN
vor <= v(v'low);
END GENERATE base_case;

induction_case: IF v'length > 1 GENERATE
CONSTANT mid : integer := (v'high + v'low)/2;
SIGNAL vor_l : std_logic;
SIGNAL vor_h : std_logic;
BEGIN
or_lo: or_vec PORT MAP(v(mid-1 DOWNTO v'low), vor_l);
or_hi: or_vec PORT MAP(v(v'high DOWNTO mid), vor_h);
vor <= vor_l or vor_h;
END GENERATE induction_case;
END ARCHITECTURE behavior;