inequality with std_logic_vector in what package is defined

Discussion in 'VHDL' started by thierrybingo, Nov 29, 2013.

  1. thierrybingo

    thierrybingo Guest

    I wonder in what packages the inequality like <, <= involving std_logic_vector operators are defined. I wrote the code below, compiled it with modelsim and it worked fine. However std_logic_1164 package does not have the defintion of < with how the result is computed?

    library ieee;
    use ieee.std_logic_1164.all;

    entity comp is
    port (a,b: in std_logic_vector(3 downto 0);
    ctr:eek:ut std_logic);
    end entity;

    architecture behaviour of comp is
    ctr<='1' when (a<b) else
    thierrybingo, Nov 29, 2013
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  2. thierrybingo

    Jim Lewis Guest

    Anytime you are doing math on vectors, you should use a math type (such as unsigned, signed, ufixed, sfixed, float, integer). For unsigned and signedI recommend using the IEEE standard package "ieee.numeric_std.all" (ratherthan the shareware package "ieee.std_logic_arith.all").

    If this is the only math usage of a and b, you can do:
    ctr<='1' when (unsigned(a) < unsigned(b)) else '0';

    If you tool supports VHDL-2008, you can get an unsigned interpretation of std_logic_vector by using "ieee.numeric_std_unsigned.all". However, over the life of a project, using a math type is a better from a documentation stand point.

    If your synthesis tool does not support VHDL-2008, you can use the shareware package, "ieee.std_logic_unsigned.all" to accomplish the same thing.

    If you use a relational and the vectors are not the same length or they contain an H or L, then the results will not match the desired numeric results.. IE: "100" > "01001" will return true. So I recommend using package "numeric_std_unsigned" to protect against this.

    Jim Lewis, Nov 30, 2013
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