clock divider quetion

[tia86]

Sorry, the thread title is "clock question" (and i know that the code is useless, is only for undestanding vhdl..)

Why this code is compiled succesfully:

entity yt is
  port (clock50 : IN std_logic;
        clko : OUT std_ulogic
);
end yt;

architecture dataflow of yt is

	signal clk :  std_logic;
begin
	process (clock50)
	begin
	 if (clock50 ='1') THEN
		clk <= '1';
	  else
		clk <= '0';
			
	end if;
	end process;

	 clko <= clk;  
     
end dataflow;

and if i change " if (clock50 ='1')" into " if (clock50'event and clock50 ='1')" the compiler report "could'nt implement registers for assignemnets on this clock edge"?
They aren't two identical examples? (the sensitivity list has only clock50 so the clock50 rising edge event is captured...).

 

[debayan_p]

Hi,

Which compiler are u using ? My ModelSim has never given me such an error !

If u use clk='1' then the sensitivity list will be triggered only when the signal value is true '1'.

But if u use (clk='1' and clk'event), then a rising edge is detected as well as its value is computed.

They say that one should always use the latter condition, if u r putting a clock on the sensitivity list, I donno why, I am not that much experienced VHDL coder. That's the way clock signals are treated.
For any other signal, the check signal='1' or '0' will suffice !

I would be happy if some exp. guy can throw some light on the clock & non-clock signal !