configurable number of interfaces

[ananth kamath]

Hello,

I need to have configurable number of interfaces in my entity. For example,

library max_package;
use max_package.all;

entity for_example is
port (
fixed: out std_logic;
variable: in std_logic_vector(0 to MAX)
);
end entity;

lets assume that MAX is defined in a max_package. Now the problem is when MAX = 0, i still have the variable port signal visible in my entity. Is there a neat way of achieving this ?

Kind Regards,
Anantha

 

[KJ]

Now the problem is when MAX = 0, i still have the variable port signal
visible in my entity. Is there a neat way of achieving this ?

1. There is nothing wrong when MAX=0, you will simply have a vector of length 1, there is no reason for it to not be visible.

2. Assuming you meant MAX=-1 (or perhaps the vector on the entity is defined to be 0 to (MAX-1)), there is still no problem. That would be a null vector.

- So, why do you think that your signal needs to not be visible on the entity?
- By the way, calling a port 'variable' won't work...that's a keyword

Kevin Jennings

 

[ananth kamath]

1. There is nothing wrong when MAX=0, you will simply have a vector of length 1, there is no reason for it to not be visible.



2. Assuming you meant MAX=-1 (or perhaps the vector on the entity is defined to be 0 to (MAX-1)), there is still no problem. That would be a null vector.



- So, why do you think that your signal needs to not be visible on the entity?

- By the way, calling a port 'variable' won't work...that's a keyword



Kevin Jennings

Using the port name as "variable" wouldn't work Thanks for the correction.
I am still a newbee in this field, so my question could be a bit lame.
If I synthesize this code, the port having NULL vectors will not be present in my entity .. is my understanding correct ? And is the result true for all synthesizers ?

Regards,
Anantha

 

[kevin.neilson]

In Synplify, if you have a port with a null range, for example:

dout: out std_logic_vector(-1 downto 0));

it will not show up as a port. This is pretty cool, actually. I don't think you can do something similar in Verilog. (For one thing, you don't specify the range direction in Verilog.) Modelsim allows this but flags a warning.

I don't know about other synthesizers. My guess would be that XST would crash and die if you give it a null range.

 

[KJ]

If I synthesize this code, the port having NULL vectors will not be present
in my entity .. is my understanding correct ? And is the result true for
all synthesizers ? Regards, Anantha

It is allowed to have a null vector on the entity. You just have to connect it to a null vector or leave it as 'open'. Either way, the vector is still listed in the port section of the entity and it can still be connected so your source code does not need to be modified for the special case.

Since it is a null vector it will not synthesize to anything. The general use for null vectors is when the vector size is controlled by a generic (like you had in your post) and a perfectly legitimate setting for that generic happens to result in not actually needing the vector.

As to 'all synthesizers', I dunno but if the one you're using doesn't support it then open a case with them and tell them that their competitiors do, you're considering switching to their tools which seem to be better supported. Quartus and Synplify support it.

Kevin Jennings

 

[ananth kamath]

Thanks a lot for the timely help. I found even XST supporting it