Confusion centered around the falling_edge

[randomdude]

I'm trying to build an IDE device and I'm having some difficulty
getting my head around why the following peice of VHDL will synthesize,
but leave the data bus at hi-z permenantly -

process(RD, WR, RST, sramreadpipe, SRAM_DATA)
begin
if RST='1' then -- if no reset in progress
if RD='1' then -- if no read in progress
DATA<=(others=>'Z'); -- high-z the bus
else -- if theres a read in progress
if falling_edge(RD) then-- check for any just-starting reads
DATA<="0101010101010101";
end if; -- ..
end if; -- ..
else
DATA<=(others=>'Z');
end if;
end process;

but if I comment out the line under 'if RD='1'' thus

process(RD, WR, RST, sramreadpipe, SRAM_DATA)
begin
if RST='1' then -- if no reset in progress
if RD='1' then -- if no read in progress
-- DATA<=(others=>'Z'); -- high-z the bus
else -- if theres a read in progress
if falling_edge(RD) then-- check for any just-starting reads
DATA<="0101010101010101";
end if; -- ..
end if; -- ..
else
DATA<=(others=>'Z');
end if;
end process;

the system behaves as expected (ie, only setting the DATA bus when
RD=0). I know I could use 'if RD='0'' instead of the falling_edge, but
this is a bad idea because I'm going to need actions only to be carried
out on the falling edge later on.. Can anyone give me a hand with this?

Ta muchly.
-Alan

 

[Ralf Hildebrandt]

I'm trying to build an IDE device and I'm having some difficulty
getting my head around why the following peice of VHDL will synthesize,
but leave the data bus at hi-z permenantly -

process(RD, WR, RST, sramreadpipe, SRAM_DATA)
begin
if RST='1' then -- if no reset in progress
if RD='1' then -- if no read in progress
DATA<=(others=>'Z'); -- high-z the bus
else -- if theres a read in progress
if falling_edge(RD) then-- check for any just-starting reads
DATA<="0101010101010101";
end if; -- ..
end if; -- ..
else
DATA<=(others=>'Z');
end if;
end process;

What you have writetn ist: "Only if RST='1! and RD='0' then a
falling_edge(RD) will be accepted."
Furthermore it is a bad idea to use RD as both asynchronous reset and clock.

Use the synchronous template:

process(reset,clock)
begin
if (reset='1' then
-- do some reset
elsif rising_edge(clock) then -- or falling_edge
-- do something
end if;
end process;


Ralf

 

[Nicolas Matringe]

Ralf Hildebrandt a écrit :
[...]

What you have writetn ist: "Only if RST='1! and RD='0' then a
falling_edge(RD) will be accepted."
Furthermore it is a bad idea to use RD as both asynchronous reset and
clock.

Use the synchronous template:

process(reset,clock)
begin
if (reset='1' then
-- do some reset
elsif rising_edge(clock) then -- or falling_edge
-- do something
end if;
end process;

I second to this and I'll add a second template for hi-Z outputs :

bidir_bus <= out_bus when output_enable = '1' else (others => 'Z');
in_bus <= to_x01(bidir_bus);

(the use of the to_x01 function is optional but very convenient when
there are weak drivers on the bus)

Nicolas