- Joined
- Nov 8, 2010
- Messages
- 3
- Reaction score
- 0
Heyy, I'm trying to do this simple factorial program but I'm having problems in the unsigned declaration. The program says to me I need put an end command, but I dont know why... please, if someone knows, subscrib =\
I'm a begginer and I need help! haha
How is the best form, in this case, to declarate the variables under architecture's declaration?
thanks for all!
waiting for answers!
hugs
Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;
entity input_out is
port( clk: IN bit);
end input_out;
architecture behavior of input_out is
begin
unsignal contador: integer;
unsignal valor: integer := 10;
unsignal n: integer := 1;
process(clk)
begin
for contador in valor downto 1 loop
n = n*contador;
end loop;
end process;
end behavior;
I'm a begginer and I need help! haha
How is the best form, in this case, to declarate the variables under architecture's declaration?
thanks for all!
waiting for answers!
hugs
Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;
entity input_out is
port( clk: IN bit);
end input_out;
architecture behavior of input_out is
begin
unsignal contador: integer;
unsignal valor: integer := 10;
unsignal n: integer := 1;
process(clk)
begin
for contador in valor downto 1 loop
n = n*contador;
end loop;
end process;
end behavior;