I have to design a fsm that reduces the frequency of the input clock by 4 (outclk=inclk/4)
I tried to do that using following vhdl code:
-------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_mod is
Port ( inclk : in STD_LOGIC;
outclk : out STD_LOGIC;
clr: in std_logic
);
end top_mod;
architecture Behavioral of top_mod is
begin
process (clr,inclk)
variable f1,f2: std_logic;
begin
if(clr='1') then
f1:='0';
f2:='0';
outclk<='0';
else
if(rising_edge(inclk)) then
if(f1='0' and f2='0') then
f1:='0'; f2:='1';
elsif(f1='0' and f2='1') then
f1:='1'; f2:='0';
elsif(f1='1' and f2='0') then
f1:='1'; f2:='1';
outclk:='1';
elsif(f1='1' and f2='1') then
f1:='0'; f2:='0';
end if;
elsif(falling_edge(inclk) and f1='1' and f2='1') then
outclk<='0';
end if;
end if;
end process;
end Behavioral;
----------------------------------
There's no problem with the syntax. But when i tried to view the RTL schematic, i encountered following error:
"Signal outclk cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."
What is wrong with my code?
Please help
:trytofly:
I tried to do that using following vhdl code:
-------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_mod is
Port ( inclk : in STD_LOGIC;
outclk : out STD_LOGIC;
clr: in std_logic
);
end top_mod;
architecture Behavioral of top_mod is
begin
process (clr,inclk)
variable f1,f2: std_logic;
begin
if(clr='1') then
f1:='0';
f2:='0';
outclk<='0';
else
if(rising_edge(inclk)) then
if(f1='0' and f2='0') then
f1:='0'; f2:='1';
elsif(f1='0' and f2='1') then
f1:='1'; f2:='0';
elsif(f1='1' and f2='0') then
f1:='1'; f2:='1';
outclk:='1';
elsif(f1='1' and f2='1') then
f1:='0'; f2:='0';
end if;
elsif(falling_edge(inclk) and f1='1' and f2='1') then
outclk<='0';
end if;
end if;
end process;
end Behavioral;
----------------------------------
There's no problem with the syntax. But when i tried to view the RTL schematic, i encountered following error:
"Signal outclk cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."
What is wrong with my code?
Please help
:trytofly: