Flip Flop Synchronization

[John]

Hi

I've heard that you can use 2 flip flops to synchronize 2 different clock
domains. Is this correct?

I've tried to do it using the following code, but the output is far from
correct. Can anyone point out what I'm doing wrong?

Thanks in advance,


FLIP FLOP
=========

entity flipflop is
Port ( D : in std_logic;
C : in std_logic;
Q : out std_logic
);
end flipflop;

architecture Behavioral of flipflop is
begin

ff : process(C)
begin
if C'event and C = '1' then
Q <= D;
end if;
end process ff;

end Behavioral;



THE PART TO DO THE SYNC
=======================

CLK is the fast clock in the first domain and SIG_IN is the slower clock in
the second domain.

entity sync is
Port ( CLK : in std_logic;
SIG_IN : std_logic;
SYNC_OUT : out std_logic
);
end sync;

architecture Behavioral of sync is
COMPONENT flipflop
PORT(
D : IN std_logic;
C : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;

signal wire : std_logic;
begin

ff0 : flipflop PORT MAP(
D => SIG_IN,
C => CLK,
Q => wire
);

ff1 : flipflop PORT MAP(
D => wire,
C => CLK,
Q => SYNC_OUT
);


end Behavioral;

 

[Niv]

The 2 FF's are used to get one clock domain signal into another clock domain
(usually faster).
The idea is to reduce metastability on the signal as it is asynchronous to
the 2nd clock domain.

Just pass the signal thru' the 2 FF's clocked by the 2nd clock. This will
reduce the chance of the
signal (at the o/p of 2nd FF) being metastable.

Note however, that metastability probability is REDUDUCED not eliminated.
More FF's reduce it further,
but it can never be zero (some mathematical equation), but in practice 2
FF's is usually enough.

In safety critical systems, the more the merrier! (If that's safe?)

Niv.

 

[EdwardH]

I'm a VHDL novice so I will just comment on what you are trying to do.
Using 2 FF's allows you to use signals from one clock domain in another
clock domain
i.e. it overcomes problems with meta-stability by reclocking signals into
the new
domain.

I am taking your words literally

CLK is the fast clock in the first domain and SIG_IN is the slower clock in
the second domain.

I have not seen this type of circuit used to reshape clocks. All it would do
is shift
the clock edge position.

In normal use of this type of circuit, SIG_IN would be a signal from the
other domain
rather than the other clock.

 

[valentin tihomirov]

Read Peter Alfke's "Moving Data Across Asynchronous Clock Boundaries" @
http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp. Here is another one
http://www.eedesign.com/editorial/2000/design0003.html.

This is not VHDL topic, though. Good Luck.