generic question

[The Weiss Family]

I've created a library of components to use in my designs.
Most of these components use "generic" widths.

For example, a 2-to-1 mux takes two std_logic_vector(width-1 downto 0)
inputs, and outputs one of them.
My question is as follows:

Is there a more generic way to describe this so that the inputs can be
std_logic?
XST doesn't seem to like std_logic_vector(0 downto 0).

Or, do I have to do what I have been doing, and define one component for
std_logic, and one for std_logic_vector?

Thanks,

Adam

 

[Allan Herriman]

I've created a library of components to use in my designs.
Most of these components use "generic" widths.

For example, a 2-to-1 mux takes two std_logic_vector(width-1 downto 0)
inputs, and outputs one of them.
My question is as follows:

Is there a more generic way to describe this so that the inputs can be
std_logic?
XST doesn't seem to like std_logic_vector(0 downto 0).

XST handles this just fine.

svl <= sl;
or
svl(0 downto 0) <= sl;

won't work, as you are trying to assign signals of different type.
This is illegal VHDL, and won't work in any proper VHDL tool, not just
XST. Your simulator, for example, wouldn't compile this either.
BTW, any reasonable design flow involves simulation before synthesis.

OTOH,
svl(0) <= sl,

will work fine, as the *elements* of the std_logic_vector have the
right type.

Or, do I have to do what I have been doing, and define one component for
std_logic, and one for std_logic_vector?

No, one copy, using std_logic_vector, is all you need.

Regards,
Allan.

 

[Jim Lewis]

I've created a library of components to use in my designs.

Most of these components use "generic" widths.

For example, a 2-to-1 mux takes two std_logic_vector(width-1 downto 0)
inputs, and outputs one of them.

An alternate solution would be to use a subprogram.
Subprograms are overloadable. You can also use an
unconstrained array.

A function works well for this as then you could write:

Y <= Mux2(Sel1, A, B) and Mux2(Sel2, C, D) ;


Cheers,
Jim
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