getting the range from a member of a record.

Discussion in 'VHDL' started by jlodman, Feb 28, 2014.

  1. jlodman

    jlodman Guest

    Why doesn't the following code compile?

    type header_t is
    record
    A : std_logic_vector(31 downto 0);
    B : std_logic_vector(39 downto 0);
    C : std_logic_vector(8 downto 0);
    D : std_logic_vector(7 downto 0);
    E : std_logic_vector(9 downto 0);
    end record;

    type compare_t is
    record
    A1 : std_logic_vector(header_t.A'LEFT downto header_t.A'RIGHT)); -- (152)
    B1 : std_logic_vector(header_t.D'LEFT downto header_t.D'RIGHT));
    C1 : std_logic_vector(header_t.E'LEFT downto header_t.E'RIGHT);
    end record;

    Modelsim gives the error for all three compare_t entries:

    # ** Warning: sorter_pkg.vhd(152): (vcom-1260) Type mark (header_t) cannot be prefix of selected name.

    The website http://www.csee.umbc.edu/portal/help/VHDL/attribute.html

    indicates that the 'LEFT and 'RIGHT can be used for any type.

    Is there another way to code this?
     
    jlodman, Feb 28, 2014
    #1
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  2. jlodman

    Dio Gratia Guest

    The following is a re-write using a package containing a shared variable to illustrate (generating a small analyzable example):

    library ieee;
    use ieee.std_logic_1164.all;

    package fum is
    type header_t is
    record
    A : std_logic_vector(31 downto 0);
    B : std_logic_vector(39 downto 0);
    C : std_logic_vector(8 downto 0);
    D : std_logic_vector(7 downto 0);
    E : std_logic_vector(9 downto 0);
    end record;

    signal foo: header_t;

    type compare_t is
    record
    A1 : std_logic_vector(foo.A'LEFT downto foo.A'RIGHT); -- (152)
    B1 : std_logic_vector(foo.D'LEFT downto foo.D'RIGHT);
    C1 : std_logic_vector(foo.E'LEFT downto foo.E'RIGHT);
    end record;

    end package;

    This analyzes successfully.

    The record type mark is not allowed as a suffix in a selected name. There is no record header_t, it's a type declaration for a record not an actual record.

    See the LRM section on selected names.

    "A selected name may be used to denote an element of a record, an object designated by an access value, or a named entity whose declaration is contained within another named entity, particularly within a library or a package."
     
    Dio Gratia, Feb 28, 2014
    #2
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  3. jlodman

    Dio Gratia Guest

    And I intended to write prefix, not suffix.
     
    Dio Gratia, Mar 1, 2014
    #3
  4. jlodman

    jlodman Guest

    So I need to create a shared variable in the package just to get at what I should be able to get at anyway? <shakes head>

    Thanks for the help!
     
    jlodman, Mar 1, 2014
    #4
  5. jlodman

    Dio Gratia Guest

    Not at all.

    And I didn't say you had to declare a shared variable. It was a demonstration of using a selected name.

    library ieee;
    use ieee.std_logic_1164.all;

    -- See IEEE Std 1076-1993 for example, 3.2.1 Array types

    package foo is
    subtype A_index_range is natural range 31 downto 0;
    subtype B_index_range is natural range 39 downto 0;
    subtype C_index_range is natural range 8 downto 0;
    subtype D_index_range is natural range 7 downto 0;
    subtype E_index_range is natural range 9 downto 0;

    type header_t is
    record
    A : std_logic_vector(A_index_range);
    B : std_logic_vector(B_index_range);
    C : std_logic_vector(C_index_range);
    D : std_logic_vector(D_index_range);
    E : std_logic_vector(E_index_range);
    end record;

    type compare_t is
    record
    A1 : std_logic_vector(A_index_range); -- (152)
    B1 : std_logic_vector(B_index_range);
    C1 : std_logic_vector(C_index_range);
    end record;

    end package;

    library ieee;
    use ieee.std_logic_1164.all;
    use work.foo.all;

    entity fum is
    end entity;

    architecture fie of fum is

    signal fee: header_t;
    signal fo: compare_t;

    signal a: std_logic_vector (A_index_range) := X"feedface" ;
    signal a1: std_logic_vector (A_index_range) := X"deadbeef" ;
    begin
    fee.A <= a;
    fo.A1 <= a1;
    end architecture;

    Which, analyzes, elaborates and runs demonstrating a lack of constraint errors for the default values for signals a and a1.

    (Consider you may have just been 'holding it wrong').
     
    Dio Gratia, Mar 1, 2014
    #5
  6. jlodman

    Andy Guest

    You could instead declare a signal or a constant (either locally or in the type's package) and use it to access the record elements' attributes.

    Andy
     
    Andy, Mar 3, 2014
    #6
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