Inout signal

Discussion in 'VHDL' started by Tianlun, Jun 30, 2003.

  1. Tianlun

    Tianlun Guest

    Hi,

    I use inout signal in my VHDL code

    Why can not I get the correct input signal?
    The input signal are already there.I can see them through logic analyser.


    entity readregister is
    Port ( fd : inout std_logic_vector(7 downto 0);
    rst:in std_logic);
    end readregister;

    architecture Behavioral of readregister is
    signal fd_s:std_logic_vector(7 downto 0);
    begin

    process(clk,rst)
    begin
    if rst='0' then
    fd<="ZZZZZZZZ";
    fd_s<="ZZZZZZZZ";
    elsif clk'event and clk='1' then
    if...
    fd_s<=fd;
    if fd_s(2)='1' then
    ....
    elsif fd_s(5)='1' then
    ...
    else
    ...
    end if;
    end if;
    end if;
    end process;
    end archtiture;





    Thanks for any valuable advice

    Tianlun
     
    Tianlun, Jun 30, 2003
    #1
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  2. Hi,

    What do you exactly mean by that? Are you seeing X's in waveform?
    Do you mean Waveform viewer?
    Normally what I do is, have an output enable, say oe_n and

    fd <= (others => 'Z') when (oe_n = '1') else fd_out;

    where fd_out is the output from this DUT.

    You didn't show the code of your TB which actually drives this fd
    (presumably in input mode to DUT, output to TB), so can't comment
    more.

    HTH,
    Ajeetha
    http://www.noveldv.com
     
    Ajeetha Kumari, Jun 30, 2003
    #2
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