Large array

Discussion in 'VHDL' started by TON2, Jan 6, 2014.

  1. TON2


    Jan 6, 2014
    Likes Received:
    In 1 clock cycle, my design output
    output_real : out std_logic_VECTOR(15 downto 0);
    I have to run my design for 2048x64 clk and store all the 2048x64 output_real to be used later.

    Problem is I tried to store the whole output in a Signal format ( array of size [2048][64][16] )but it is too large, is there any alternative solutions?
    I'm thinking of writing it into a table but not sure how to do it.

    Thanks in advance for advice!
    TON2, Jan 6, 2014
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