Hello,
i have two vhdl prog
FIFO(RTL)
entity2(arch2)
I see these programs in project windows of quartus 2.
i have another prog bench in vhdl
this vhdl bench is aimed by quartus in tool-simulation-bench
The software simulation is modelsim altera
when can i make a link betwen the signal (vhdl bench )
and the in/out of entitys
In bench vhdl i try :
LED_FIFO : FIFO use entity work.FIFO(RTL);
HED_FIFO : FIFO use entity work.FIFO(RTL);
LED_fifo: map(
link
in/out=>signal
)
quartus don't find component FIFO.
Please help.
Thanks
i have two vhdl prog
FIFO(RTL)
entity2(arch2)
I see these programs in project windows of quartus 2.
i have another prog bench in vhdl
this vhdl bench is aimed by quartus in tool-simulation-bench
The software simulation is modelsim altera
when can i make a link betwen the signal (vhdl bench )
and the in/out of entitys
In bench vhdl i try :
LED_FIFO : FIFO use entity work.FIFO(RTL);
HED_FIFO : FIFO use entity work.FIFO(RTL);
LED_fifo: map(
link
in/out=>signal
)
quartus don't find component FIFO.
Please help.
Thanks