Multiplier synthesis on vhdl

Discussion in 'VHDL' started by zenerz, May 25, 2008.

  1. zenerz

    zenerz

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    Hello!

    Got a huge problem with a design. Im working on a project with a spartan 3 3s200ft256 and this fpga has 12 multipliers of 18x18. Well the question is all about this line of code...
    Img_addr<= std_logic_vector(Img_size_x * std_logic_vector(to_unsigned( j+ n, 8 ))+m + k -1);

    img_size_x is std_logic_vector, j, n, m, k are integer variables on a process.
    (8 bits slv * 8 bits slv)

    Does this sentence infers one multiplier on synthesis?. The functional model is ok, but dunno if im going to find error on synthesis. I read somewhere that Leonardo modgen automatically recognizes the operator * and infers and synthetises the multiplier.
    Does Leonardo Spectrum do the "trick" or i have to declare the multiplier and instantiate it?

    Please, help me out
     
    Last edited: May 26, 2008
    zenerz, May 25, 2008
    #1
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