M
Mark McDougall
Hi all,
I'm currently doing the top-level entity for an fpga and the idea is for
the port names to match the schematic names.
However, the schematic has non-contiguous indexes for a bunch of
signals. For example...
CTS has [1:5],[7] & [9:10]
I know you can't do...
entity blah is
port
(
cts : in std_logic_vector(10 downto 9);
cts : in std_logic_vector(7 downto 7);
cts : in std_logic_vector(5 downto 1);
...
};
but is there any way of using a range such as
cts : in std_logic_vector(10 downto 9, 7, 5 downto 1);
or something similar???
My only other thought is to use
cts10 : in std_logic;
cts9 : in std_logic;
cts7 : in std_logic; ... etc
Regards,
I'm currently doing the top-level entity for an fpga and the idea is for
the port names to match the schematic names.
However, the schematic has non-contiguous indexes for a bunch of
signals. For example...
CTS has [1:5],[7] & [9:10]
I know you can't do...
entity blah is
port
(
cts : in std_logic_vector(10 downto 9);
cts : in std_logic_vector(7 downto 7);
cts : in std_logic_vector(5 downto 1);
...
};
but is there any way of using a range such as
cts : in std_logic_vector(10 downto 9, 7, 5 downto 1);
or something similar???
My only other thought is to use
cts10 : in std_logic;
cts9 : in std_logic;
cts7 : in std_logic; ... etc
Regards,