Reflexions about a new HDL language

Discussion in 'VHDL' started by Mister_J, Aug 30, 2013.

  1. Mister_J

    Mister_J

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    Hello,

    I am thinking about defining a new HDL language, that will be more modern than VHDL (and Verilog) and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. In short, it will be like an enhanced VHDL language that aims to be especially attractive for VHDL developpers. I also would like to write its compiler in Ada.
    I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not :).

    Anyways, I made a document with my first reflexions for this new language. I currently don't have the right to post links because I need a few more posting. So to have the link, remove the spaces of :
    http :// hdl-eesi.rhcloud . com

    I think it's a good idea to ask for feedback before I go too far :), so what are your feedbacks ?

    Cheers,
    Jonas
     
    Mister_J, Aug 30, 2013
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  2. Mister_J

    simguru

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    You don't want a new HDL, just add the essential features to C++ - a quick hack a clang will do that.

    Check out my parallel.cc website for extension ideas.

    Kev.
     
    simguru, Oct 19, 2013
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