Signals in VHDL

S

Sushma

Below is my VHDL code. I am unable to have any success with signals
like CA0,CA1 and CA2.S0,S1 and S2. What am I doing wrong?


library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

ENTITY gates_backup1 IS
PORT
(
SWRESET :INOUT STD_LOGIC;
SER_EN :INOUT STD_ULOGIC;
MCLK :IN std_ulogic;
CLK_100 :IN STD_LOGIC;
CLK_IN :IN STD_LOGIC;
HOLD_EN :INOUT STD_LOGIC;
POST_EN :INOUT STD_LOGIC;
SD_CLK :OUT STD_LOGIC;
SD_IN :OUT STD_LOGIC;
SD_LOAD :OUT STD_LOGIC;
DISGCLK :INOUT STD_LOGIC;
CLK_OUT :INOUT
STD_LOGIC;
A0 :INOUT STD_LOGIC;
A1 :INOUT STD_LOGIC;
A2 :INOUT STD_LOGIC;
A3 :INOUT STD_LOGIC;
A10 :INOUT STD_LOGIC;
A11 :INOUT STD_LOGIC;
A12 :INOUT STD_LOGIC;
TEST01 :INOUT STD_LOGIC;
TEST02 :INOUT STD_LOGIC;
TEST03 :INOUT STD_LOGIC;
TEST04 :INOUT STD_LOGIC;
TEST05 :INOUT STD_LOGIC;
TEST06 :INOUT STD_LOGIC;
TEST07 :INOUT STD_LOGIC;
AD1 :INOUT STD_LOGIC;
CLK_SRC :INOUT STD_LOGIC;
IO_WR :INOUT STD_LOGIC;
AD3 :INOUT STD_LOGIC;
IO_RD :INOUT STD_LOGIC;
D12 :INOUT STD_LOGIC
);
END gates_backup1;

ARCHITECTURE behavior OF gates_backup1 IS


SIGNAL P12 :STD_LOGIC;
SIGNAL CA0 :STD_LOGIC;
SIGNAL TC_128 :STD_LOGIC;
SIGNAL LOAD_CNT :STD_LOGIC;
SIGNAL LOAD_ZER :STD_LOGIC;
SIGNAL LOAD_SEL :STD_LOGIC;
SIGNAL CA1 :STD_LOGIC;
SIGNAL CA2 :STD_LOGIC;
SIGNAL TC_1K :STD_LOGIC;
SIGNAL TC_2K :STD_LOGIC;
SIGNAL TC_4K :STD_LOGIC;
SIGNAL CH_EN :STD_LOGIC;
SIGNAL ST_CLK :STD_LOGIC;
SIGNAL CH_SEL :STD_LOGIC;
SIGNAL IO_EN :STD_LOGIC;
SIGNAL SWRESET_CLK :STD_LOGIC;
SIGNAL S0 :STD_LOGIC;
SIGNAL S1 :STD_LOGIC;
SIGNAL S2 :STD_LOGIC;
SIGNAL RD_BUSY :STD_LOGIC;




BEGIN

---------------------------------------------------------------
PROCESS(CA0,A0,A1,A2,A3)
BEGIN
CA0 <= A0 AND A1 AND A2 AND A3;
TC_1K <= CA0 AND CA1 AND CA2;
TC_2K <= A10 AND TC_1K;
TC_4K <= A10 AND A11 AND TC_1K;
TEST01 <= CA0;
TEST02 <= CA1;
TEST03 <= CA2;
TEST04 <= TC_1K;
TEST05 <= TC_2K;
TEST06 <= TC_4K;
END PROCESS;

------------------------------------------------------------------
PROCESS(SWRESET,MCLK,S2,S1,S0,HOLD_EN,POST_EN,CA0,CA1)
BEGIN
IF(SWRESET='0')THEN
P12 <='0';
ELSIF(MCLK'EVENT AND MCLK='1')THEN
P12 <= D12;
END IF;
LOAD_SEL <= NOT(S2) AND NOT(S1) AND HOLD_EN;
LOAD_ZER <= (NOT(S2) AND NOT(S1) AND HOLD_EN)OR(S2 AND S1 AND
NOT(S0))OR(POST_EN);
TC_128 <= CA0 AND CA1;
END PROCESS;

process(MCLK)
begin
if MCLK = '1' and MCLK'event then
TEST07 <= P12;
end if;
end process;

------------------------------------------------------------------------

PROCESS(D8,SWRESET_CLK,CH_SEL,AD3,IO_WR,IO_RD)
BEGIN
IF(SWRESET_CLK'EVENT AND SWRESET_CLK='1')THEN
SWRESET <= D8;
END IF;
ST_CLK <= NOT(CH_SEL AND NOT(AD3) AND NOT(IO_WR));
IO_EN <= (NOT(IO_RD) AND CH_SEL AND AD3) OR (NOT(IO_WR) AND CH_SEL
AND AD3);
SWRESET_CLK <= NOT(CH_SEL AND NOT(AD3) AND NOT(IO_WR));
RD_BUSY <= NOT(IO_RD) AND NOT(AD3) AND CH_SEL;
END PROCESS;

END behavior;
 
M

Mike Treseler

Sushma said:
Below is my VHDL code. I am unable to have any success with signals
like CA0,CA1 and CA2.S0,S1 and S2. What am I doing wrong?
Click to expand...

vcom gates.vhd
** Error: gates.vhd(112): (vcom-1136) Unknown identifier "d8".
** Error: gates.vhd(112): Expression is not a signal.
** Error: gates.vhd(115): (vcom-1136) Unknown identifier "d8".
** Error: gates.vhd(124): VHDL Compiler exiting
 
S

Sushma

vcom gates.vhd
** Error: gates.vhd(112): (vcom-1136) Unknown identifier "d8".
** Error: gates.vhd(112): Expression is not a signal.
** Error: gates.vhd(115): (vcom-1136) Unknown identifier "d8".
** Error: gates.vhd(124): VHDL Compiler exiting
Click to expand...

Mike:
Thanks for the reply. I defined D8. I am not getting any errors in
my code. I am just not able to get my signals work. Please help

Thanks
Sushma
 
J

Jim Lewis

Sushma
You don't have to put your signal assignments in
a process. If you put them in a process, signals
on the right hand side of an expression must be on the
sensitivity list. See marked code below.

Regards,
Jim Lewis
SynthWorks VHDL Training
www.synthworks.com
Below is my VHDL code. I am unable to have any success with signals
like CA0,CA1 and CA2.S0,S1 and S2. What am I doing wrong?


library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;

ENTITY gates_backup1 IS
PORT
(
SWRESET :INOUT STD_LOGIC;
SER_EN :INOUT STD_ULOGIC;
MCLK :IN std_ulogic;
CLK_100 :IN STD_LOGIC;
CLK_IN :IN STD_LOGIC;
HOLD_EN :INOUT STD_LOGIC;
POST_EN :INOUT STD_LOGIC;
SD_CLK :OUT STD_LOGIC;
SD_IN :OUT STD_LOGIC;
SD_LOAD :OUT STD_LOGIC;
DISGCLK :INOUT STD_LOGIC;
CLK_OUT :INOUT
STD_LOGIC;
A0 :INOUT STD_LOGIC;
A1 :INOUT STD_LOGIC;
A2 :INOUT STD_LOGIC;
A3 :INOUT STD_LOGIC;
A10 :INOUT STD_LOGIC;
A11 :INOUT STD_LOGIC;
A12 :INOUT STD_LOGIC;
TEST01 :INOUT STD_LOGIC;
TEST02 :INOUT STD_LOGIC;
TEST03 :INOUT STD_LOGIC;
TEST04 :INOUT STD_LOGIC;
TEST05 :INOUT STD_LOGIC;
TEST06 :INOUT STD_LOGIC;
TEST07 :INOUT STD_LOGIC;
AD1 :INOUT STD_LOGIC;
CLK_SRC :INOUT STD_LOGIC;
IO_WR :INOUT STD_LOGIC;
AD3 :INOUT STD_LOGIC;
IO_RD :INOUT STD_LOGIC;
D12 :INOUT STD_LOGIC
);
END gates_backup1;

ARCHITECTURE behavior OF gates_backup1 IS


SIGNAL P12 :STD_LOGIC;
SIGNAL CA0 :STD_LOGIC;
SIGNAL TC_128 :STD_LOGIC;
SIGNAL LOAD_CNT :STD_LOGIC;
SIGNAL LOAD_ZER :STD_LOGIC;
SIGNAL LOAD_SEL :STD_LOGIC;
SIGNAL CA1 :STD_LOGIC;
SIGNAL CA2 :STD_LOGIC;
SIGNAL TC_1K :STD_LOGIC;
SIGNAL TC_2K :STD_LOGIC;
SIGNAL TC_4K :STD_LOGIC;
SIGNAL CH_EN :STD_LOGIC;
SIGNAL ST_CLK :STD_LOGIC;
SIGNAL CH_SEL :STD_LOGIC;
SIGNAL IO_EN :STD_LOGIC;
SIGNAL SWRESET_CLK :STD_LOGIC;
SIGNAL S0 :STD_LOGIC;
SIGNAL S1 :STD_LOGIC;
SIGNAL S2 :STD_LOGIC;
SIGNAL RD_BUSY :STD_LOGIC;




BEGIN

---------------------------------------------------------------
Click to expand...
-- remove > PROCESS(CA0,A0,A1,A2,A3)
-- remove > BEGIN
CA0 <= A0 AND A1 AND A2 AND A3;
TC_1K <= CA0 AND CA1 AND CA2;
TC_2K <= A10 AND TC_1K;
TC_4K <= A10 AND A11 AND TC_1K;
TEST01 <= CA0;
TEST02 <= CA1;
TEST03 <= CA2;
TEST04 <= TC_1K;
TEST05 <= TC_2K;
TEST06 <= TC_4K; -- remove > END PROCESS;

------------------------------------------------------------------ -- change sensitivity list to:
PROCESS(SWRESET,MCLK)
BEGIN
IF(SWRESET='0')THEN
P12 <='0';
ELSIF(MCLK'EVENT AND MCLK='1')THEN
P12 <= D12;
END IF;
END PROCESS;
Click to expand...

-- move these outside process.
> LOAD_SEL <= NOT(S2) AND NOT(S1) AND HOLD_EN;
> LOAD_ZER <= (NOT(S2) AND NOT(S1) AND HOLD_EN)OR(S2 AND S1 AND
> NOT(S0))OR(POST_EN);
> TC_128 <= CA0 AND CA1;

process(MCLK)
begin
if MCLK = '1' and MCLK'event then
TEST07 <= P12;
end if;
end process;

------------------------------------------------------------------------
-- Change sensitivity list to:
PROCESS(SWRESET_CLK)
BEGIN
IF(SWRESET_CLK'EVENT AND SWRESET_CLK='1')THEN
SWRESET <= D8;
END IF;
END PROCESS;
Click to expand...

-- move these outside process.
 
S

Sushma

Sushma
You don't have to put your signal assignments in
a process. If you put them in a process, signals
on the right hand side of an expression must be on the
sensitivity list. See marked code below.

Regards,
Jim Lewis
SynthWorks VHDL Trainingwww.synthworks.com










-- remove > PROCESS(CA0,A0,A1,A2,A3)
-- remove > BEGIN> CA0 <= A0 AND A1 AND A2 AND A3;

-- remove > END PROCESS;


-- change sensitivity list to:


-- move these outside process.



-- Change sensitivity list to:


-- move these outside process.

- Show quoted text -- Hide quoted text -

- Show quoted text -
Click to expand...

Hello Jim:

I made the changes but still the same. My signals do not work.
CA0,CA1, CA2, S0,S1 and S2

Thanks
Sushma
 
M

Mike Treseler

Sushma said:
I made the changes but still the same. My signals do not work.
CA0,CA1, CA2, S0,S1 and S2
Click to expand...

If it were my job to solve your problem,
I would write a testbench, look at the waves
and debug the code.

-- Mike Treseler
 
D

Dave Pollum

If it were my job to solve your problem,
I would write a testbench, look at the waves
and debug the code.

-- Mike Treseler
Click to expand...

At the very least, look at the RTL schematic. Perhaps CA0, etc get
optimized away by the VHDL compiler. And as Mike said, write a
testbench and see what the results are.
-Dave Pollum
 
Q

quantum_dot

Joined
Nov 21, 2006
Messages
31
Reaction score
0
Hi Sushma,
I can see that you have not initialiazed your signals to any value ( 0 or 1 ). Plz initialize them at power on reset and then check the results

:driver:
 
A

Ahmed Samieh

Below is my VHDL code. I am unable to have any success with signals
like CA0,CA1 and CA2.S0,S1 and S2. What am I doing wrong?
Click to expand...
SIGNAL CA0 :STD_LOGIC; -- remove
SIGNAL TC_128 :STD_LOGIC;
........
SIGNAL CA1 :STD_LOGIC;
SIGNAL CA2 :STD_LOGIC;
SIGNAL TC_1K :STD_LOGIC; -- remove
SIGNAL TC_2K :STD_LOGIC; -- remove
SIGNAL TC_4K :STD_LOGIC; -- remove
.......

BEGIN

---------------------------------------------------------------
PROCESS(CA0,A0,A1,A2,A3)
BEGIN
CA0 <= A0 AND A1 AND A2 AND A3;
TC_1K <= CA0 AND CA1 AND CA2;
TC_2K <= A10 AND TC_1K;
TC_4K <= A10 AND A11 AND TC_1K;
TEST01 <= CA0;
TEST02 <= CA1;
TEST03 <= CA2;
TEST04 <= TC_1K;
TEST05 <= TC_2K;
TEST06 <= TC_4K;
END PROCESS;
Click to expand...

use variables instead of signals for CA0,TC_1K,TC_2K,TC_4K
and modify the sensitivity list
PROCESS(A0,A1,A2,A3,CA1,CA2,A10,A11)
VARIABLE CA0,TC_1K,TC_2K,TC_4K : std_logic;
BEGIN
CA0 := A0 AND A1 AND A2 AND A3;
TC_1K := CA0 AND CA1 AND CA2;
TC_2K := A10 AND TC_1K;
TC_4K := A10 AND A11 AND TC_1K;
TEST01 <= CA0;
TEST02 <= CA1;
TEST03 <= CA2;
TEST04 <= TC_1K;
TEST05 <= TC_2K;
TEST06 <= TC_4K;
END PROCESS;

do it with all processes,
search for (Signal Assignment Versus Variable Assignment)

Ahmed Samieh
 

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