For some reason I can't seem to find a clear answer for this. Are all VHDL operators overloaded to allow signed arithmetic?
I want to use std_logic_vectors to do add and multiply over. But if I use: "result <= signed(data_a) + signed(data_b)", does the numeric_std library account for overflow and saturate? By the way, my output, result, needs to be a std_logic_vector, so would doing this work (as long as they line up)?
Likewise, with multiply. I haven't even been able to find whether you can do multiply with the * operator.
Thanks for the help!
I want to use std_logic_vectors to do add and multiply over. But if I use: "result <= signed(data_a) + signed(data_b)", does the numeric_std library account for overflow and saturate? By the way, my output, result, needs to be a std_logic_vector, so would doing this work (as long as they line up)?
Likewise, with multiply. I haven't even been able to find whether you can do multiply with the * operator.
Thanks for the help!