SR Flip Flop

Discussion in 'VHDL' started by RishiD, Oct 29, 2006.

  1. RishiD

    RishiD Guest

    Hi,

    Just started learning VHDL, and trying to code up a S-R Flip flop with
    async reset.

    Here is what I got, believe this is correct.

    Any thing I am missing?

    Thanks,

    RishiD

    achitecture SR of SRFF is
    signal Qint : STD_LOGIC;
    begin
    process (clk, reset) begin
    if (reset = '1' and s = '1') then
    Qint <= 'X';
    elsif (reset = '1' and s = '0') then
    Qint <= '0';
    elsif (clk'event AND clk = '1') then
    if (s = '1') then
    Qint <= '1';
    end if;
    end if;
    end process;
    Q <= Qint;
    end SR;
     
    RishiD, Oct 29, 2006
    #1
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  2. RishiD

    phong

    Joined:
    Oct 26, 2006
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    achitecture SR of SRFF is
    signal Qint : STD_LOGIC;
    begin
    process (clk, reset) begin
    if (reset = '1') then
    Qint <= '0'; -- or '1';
    elsif (clk'event AND clk = '1') then
    if (s = '1') then Qint <= '1';
    else Qint <= Qint;
    end if;
    end if;
    end process;
    Q <= Qint;
    end SR;
     
    phong, Oct 29, 2006
    #2
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  3. SR-flipflop? Unfortunately there is no unique meaning behind this word.

    Usually it is called RS-flipflop. Unfortunately a lot of professors do
    not mean and edge-sensitive register (a flipflop) with this, but a
    "RS-latch" - a level sensitive register.

    If you really mean a flipflop there is the possibility of
    * both async set and reset
    * one async set or reset and one sync reset or set
    * both sync set and reset.
    You try to model a flipflop with async reset and sync set. But why do
    you try to assign an 'X' to Qint if the synchronous set and the
    asynchronous reset are active? For the RS-latch it is forbidden to
    activate the async set and the async reset simultaneously. But for a
    flipflop?

    Furthermore two RS-latches forming a master/slave flipflop are quite
    uncommon in todays cell libraries. D-type flipflops are common.

    -- D-flipflop with async set+reset and sync set/reset:
    process (clk, async_reset, async_set) begin
    if (async_reset='1') then
    Qint <= '0';
    elsif (async_set = '1') then
    Qint <= '1';
    elsif (clk'event AND clk = '1') then
    if (sync_set = '1') then
    Qint <= '1';
    elsif (sync_reset='1') then
    Qint <='0';
    else
    Qint <= data_in;
    end if;
    end if;


    Ralf
     
    Ralf Hildebrandt, Oct 30, 2006
    #3
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