Hi all
I am having a problem with the gate-level VHDL file that Synopsys Design compiler produces after synthesis. Specifically, I am giving the following commands:
change_names -rules vhdl -hierarchy
write -hierarchy -format vhdl topdesign -output myfile.vhd
The VHDL file produced has a problem. In many cases, ports that are declared as type "out" are being used on the right side of signal assignment. For example, something like this is happening:
entity example is
port(ahbo: out std_logic_vector (3 downto 0).....
end example
architecture rtl of entity is
begin
.....
ahbo <= (ahbo(3), ahbo(2), ahbo(1), ahbo(0));
end rtl
Of course, when I try to simulate this post-synthesis netlist in ModeSim, it complains...does anyone know why this is happening and how I can get rid of it?
Thanks!
I am having a problem with the gate-level VHDL file that Synopsys Design compiler produces after synthesis. Specifically, I am giving the following commands:
change_names -rules vhdl -hierarchy
write -hierarchy -format vhdl topdesign -output myfile.vhd
The VHDL file produced has a problem. In many cases, ports that are declared as type "out" are being used on the right side of signal assignment. For example, something like this is happening:
entity example is
port(ahbo: out std_logic_vector (3 downto 0).....
end example
architecture rtl of entity is
begin
.....
ahbo <= (ahbo(3), ahbo(2), ahbo(1), ahbo(0));
end rtl
Of course, when I try to simulate this post-synthesis netlist in ModeSim, it complains...does anyone know why this is happening and how I can get rid of it?
Thanks!