H
hssig
Hi,
for synthesis we often face the situation that we have to write a
wrapper with input and output registers to see what the performance
etc. of the module looks like.
For example:
entity test_module is
port( Clk : in std_logic;
i_Data : in std_logic_vector(7 downto 0);
o_Data : out std_logic_vector(7 downto 0)
);
end test_module;
architecture rtl of test_module is
....
end rtl;
------------------------------------------------------------------------
The wrapper:
entity wrap_test_module is
port( Clk : in std_logic;
i_Data : in std_logic_vector(7 downto 0);
o_Data: out std_logic_vector(7 downto 0)
);
end wrap_test_module;
architecture wrapper of wrap_test_module is
component test_module ...
signal l_data_in, l_i_test_Data : std_logic_vector(7 downto 0);
begin
process(Clk)
begin
wait until rising_edge(Clk);
l_data_in <= i_Data;
o_Data <= l_i_test_Data;
end process;
i_test : test_module
port map ( Clk => Clk,
i_Data => l_data_in,
o_Data => l_i_test_Data
);
end wrapper;
Is there some possibility to introduce some automatism to create those
kind of wrappers ?
Has someone done that kind of job, for example with TCL ?
Cheers,
hssig
for synthesis we often face the situation that we have to write a
wrapper with input and output registers to see what the performance
etc. of the module looks like.
For example:
entity test_module is
port( Clk : in std_logic;
i_Data : in std_logic_vector(7 downto 0);
o_Data : out std_logic_vector(7 downto 0)
);
end test_module;
architecture rtl of test_module is
....
end rtl;
------------------------------------------------------------------------
The wrapper:
entity wrap_test_module is
port( Clk : in std_logic;
i_Data : in std_logic_vector(7 downto 0);
o_Data: out std_logic_vector(7 downto 0)
);
end wrap_test_module;
architecture wrapper of wrap_test_module is
component test_module ...
signal l_data_in, l_i_test_Data : std_logic_vector(7 downto 0);
begin
process(Clk)
begin
wait until rising_edge(Clk);
l_data_in <= i_Data;
o_Data <= l_i_test_Data;
end process;
i_test : test_module
port map ( Clk => Clk,
i_Data => l_data_in,
o_Data => l_i_test_Data
);
end wrapper;
Is there some possibility to introduce some automatism to create those
kind of wrappers ?
Has someone done that kind of job, for example with TCL ?
Cheers,
hssig