Variables instead of signals: what about constraints?

Discussion in 'VHDL' started by Cesar, Sep 21, 2010.

  1. Cesar

    Cesar Guest

    It's some months since I've been coding my VHDL modules within a
    single process. It's being a good experience but I've come across with
    a problem. When I try to attach a constraint like KEEP or IOB to a
    net, I've realized that there is no way to assign it to a variable,
    you can only do it to signals.
    Any solution?

    Regards,
    César
     
    Cesar, Sep 21, 2010
    #1
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  2. Cesar

    rickman Guest

    To bring a value out of a process you have to use signals. To reach
    an IOB then you would have a signal to attach the constraint to,
    right?

    If you are using a constraint like KEEP, the question is why? The
    other question is, why not use a signal? You are not forced to use
    variables in processes.

    Rick
     
    rickman, Sep 21, 2010
    #2
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  3. Cesar

    Andy Guest

    Other than simply a limitation of the synthesis tool, I can see some
    potential problems with having some constraints applied to a variable.

    In a clocked process, multiple accesses to the same variable may imply
    combinatorial and registered data, which are mapped to different
    resources. If you applied a constraint to the variable, to which
    resource would you want to apply the constraint? In a clocked process,
    any signal that is assigned always becomes a register, and the
    constraint applied would map to the same resource.

    Are you needing to keep a combinatorial signal, or a register? If the
    former, you may need to fall back to a combinatorial process (or
    concurrent assignment) and use a vhdl signal for it.

    If you need to keep a register, you can create a duplicate of the
    register with a signal (or just code it with the signal instead of the
    variable), and keep that.

    If the item you need to keep is a combinatorial function of registered
    values within the same process, some tools allow you so specify output
    signals in clocked processes that are combinatorial functions of
    registered variables.

    process (clk) is
    variable myvar : natural range 0 to 7;
    begin
    if rising_edge(clk) then
    myvar := (myvar + 1) mod 8;
    outputa <= myfunc(myvar);
    end if;
    outputb <= myfunc(myvar);
    end process;

    In the above, outputa becomes the registered function of the
    combinatorial version of myvar. Outputb becomes the combinatorial
    function of the registered version of myvar. If both functions are the
    same, some synthesis tools will optimize both into one output (I've
    seen simplify choose the registered output)

    Andy
     
    Andy, Sep 21, 2010
    #3
  4. Cesar

    Cesar Guest

    I'm double-flopping an input signal and I want to avoid implementing
    it as a LUT shift-register, because a LUT shift-register has a longer
    clock-to-output than a CLB flip-flop.
    The way to do it is to apply a KEEP or NOMERGE constraint to the first
    flip-flop output.

    Just to be style consistent.

    Regards,
    César
     
    Cesar, Sep 22, 2010
    #4
  5. Cesar

    Cesar Guest

    This is my case. I'll do that. Any way, it's not nice to modify the
    VHDL code to assign a constraint.
     
    Cesar, Sep 22, 2010
    #5
  6. An Fmax timing constraint would cover
    all the internal registers, including
    those input registers.

    To avoid fanout duplication on the
    second synchronization register,
    I code for three input registers.
    |
    .-[DQ]->

    Otherwise, I have to somehow verify
    no register duplication on the second stage.


    -- Mike Treseler
     
    Mike Treseler, Sep 22, 2010
    #6
  7. Cesar

    rickman Guest

    You lost me somewhere. The first flop "sees" the async signal. The
    second flop sees a stable, sync signal. Why can't the second flop be
    duplicated? As long as there is adequate slack time in all paths
    between the first flop and the second rank of flops, how would it make
    a problem to have multiple flops in the second rank? I agree that the
    first flop must not be duplicated or you have lost the value of the
    exercise.

    Also, how does the third rank of flops prevent duplication of the
    first?

    Did I miss something in metastability 101?

    Rick
     
    rickman, Sep 23, 2010
    #7
  8. Often this is true, but sometimes there isn't enough slack time without
    a special constraint. The second flop always provides enough slack time.

    My goal is bomb-proof synchronization using only an Fmax constraint.
    The point is that if the third flop *is* duplicated,
    I still have two flops dedicated to synchronization.


    -- Mike Treseler
     
    Mike Treseler, Sep 23, 2010
    #8
  9. Cesar

    Pontus Guest

    If you mean you want to "decorate" a signal with an attribute of some
    type,
    you must do so in the declarative part of your signals.
    Since your architecture is free of any signal declarations,
    you cant declare or "attach" the attributes there.
    However you can both declare and attach attributes to signals in the
    entity ports within the entity declaration itself.

    Untested code:

    entity e is
    port (
    my_out : out bit);
    begin
    attribute syn_allow_retiming : boolean;
    attribute syn_allow_retiming of my_out : signal is false;
    end entity e;

    HTH -- Pontus
     
    Pontus, Sep 26, 2010
    #9
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