Hello,
I'm trying to modify and convert Sobel description from Verilog to VHDL. However when it comes to output from bigger array to smaller array, I faced some difficulty to descripte it. Could anyone tell me how to convert this line in VHDL?
"assign out = (|sum[10:8])?8'hff : sum[7:0];"
Sobel In Verilog desription:
module sobel( p0, p1, p2, p3, p5, p6, p7, p8, out);
input [7:0] p0,p1,p2,p3,p5,p6,p7,p8; // 8 bit pixels inputs
output [7:0] out; // 8 bit output pixel
wire signed [10:0] gx,gy; //11 bits because max value of gx and gy is
//255*4 and last bit for sign
wire signed [10:0] abs_gx,abs_gy; //it is used to find the absolute value of gx and gy
wire [10:0] sum; //the max value is 255*8. here no sign bit needed.
assign gx=((p2-p0)+((p5-p3)<<1)+(p8-p6));//sobel mask for gradient in horiz. direction
assign gy=((p0-p6)+((p1-p7)<<1)+(p2-p8));//sobel mask for gradient in vertical direction
assign abs_gx = (gx[10]? ~gx+1 : gx); // to find the absolute value of gx.
assign abs_gy = (gy[10]? ~gy+1 : gy); // to find the absolute value of gy.
assign sum = (abs_gx+abs_gy); // finding the sum
assign out = (|sum[10:8])?8'hff : sum[7:0]; // to limit the max value to 255
endmodule
Sobel In VHDL description:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sobel is
Port(
Xnm1Ynm1 : in std_logic_vector ( 7 downto 0 );
XnYnm1 : in std_logic_vector ( 7 downto 0 );
Xnp1Ynm1 : in std_logic_vector ( 7 downto 0 );
Xnm1Yn : in std_logic_vector ( 7 downto 0 );
XnYn : in std_logic_vector ( 7 downto 0 );
Xnp1Yn : in std_logic_vector ( 7 downto 0 );
Xnm1Ynp1 : in std_logic_vector ( 7 downto 0 );
XnYnp1 : in std_logic_vector ( 7 downto 0 );
Xnp1Ynp1 : in std_logic_vector ( 7 downto 0 );
ydata_out : out std_logic_vector ( 7 downto 0 ));
end Sobel;
architecture Behavioral of Sobel is
signal op_int_vaL1 : integer;
signal op_int_vaL2 : integer;
signal op_vaL1 : integer;
signal op_vaL2 : integer;
signal abs_op_int_vaL1 : std_logic_vector (10 downto 0);
signal abs_op_int_vaL2 : std_logic_vector (10 downto 0);
signal sum : std_logic_vector (10 downto 0);
constant Xnm1Ynm1VaL1 : integer := -1;
constant XnYnm1VaL1 : integer := 0;
constant Xnp1Ynm1VaL1 : integer := 1;
constant Xnm1YnVaL1 : integer := -2;
constant XnYnVaL1 : integer := 0;
constant Xnp1YnVaL1 : integer := 2;
constant Xnm1Ynp1VaL1 : integer := -1;
constant XnYnp1VaL1 : integer := 0;
constant Xnp1Ynp1VaL1 : integer := 1;
constant Xnm1Ynm1VaL2 : integer := -1;
constant XnYnm1VaL2 : integer := -2;
constant Xnp1Ynm1VaL2 : integer := -1;
constant Xnm1YnVaL2 : integer := 0;
constant XnYnVaL2 : integer := 0;
constant Xnp1YnVaL2 : integer := 0;
constant Xnm1Ynp1VaL2 : integer := 1;
constant XnYnp1VaL2 : integer := 2;
constant Xnp1Ynp1VaL2 : integer := 1;
begin
op_int_vaL1 <= Xnm1Ynm1VaL1*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL1*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL1*CONV_INTEGER(Xnp1Ynm1)
+ Xnm1YnVaL1*CONV_INTEGER(Xnm1Yn) + XnYnVaL1*CONV_INTEGER(XnYn) + Xnp1YnVaL1*CONV_INTEGER(Xnp1Yn)
+ Xnm1Ynp1VaL1*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL1*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL1*CONV_INTEGER(Xnp1Ynp1);
op_int_vaL2 <= Xnm1Ynm1VaL2*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL2*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL2*CONV_INTEGER(Xnp1Ynm1)
+ Xnm1YnVaL2*CONV_INTEGER(Xnm1Yn) + XnYnVaL2*CONV_INTEGER(XnYn) + Xnp1YnVaL2*CONV_INTEGER(Xnp1Yn)
+ Xnm1Ynp1VaL2*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL2*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL2*CONV_INTEGER(Xnp1Ynp1);
op_vaL1 <= abs(op_int_vaL1);
op_vaL2 <= abs(op_int_vaL2);
abs_op_int_vaL1 <= CONV_std_logic_vector (op_vaL1, 11);
abs_op_int_vaL2 <= CONV_std_logic_vector (op_vaL2, 11);
sum <= abs_op_int_vaL2 + abs_op_int_vaL1;
process(sum)
if (sum > '00011111111') then
ydata_out <= "11111111";
else
ydata_out <= sum (7 downto 0);
end if;
end process;
end Behavioral;
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compile error happened in line process(sum). Thanks for your attend of reading this post.
I'm trying to modify and convert Sobel description from Verilog to VHDL. However when it comes to output from bigger array to smaller array, I faced some difficulty to descripte it. Could anyone tell me how to convert this line in VHDL?
"assign out = (|sum[10:8])?8'hff : sum[7:0];"
Sobel In Verilog desription:
module sobel( p0, p1, p2, p3, p5, p6, p7, p8, out);
input [7:0] p0,p1,p2,p3,p5,p6,p7,p8; // 8 bit pixels inputs
output [7:0] out; // 8 bit output pixel
wire signed [10:0] gx,gy; //11 bits because max value of gx and gy is
//255*4 and last bit for sign
wire signed [10:0] abs_gx,abs_gy; //it is used to find the absolute value of gx and gy
wire [10:0] sum; //the max value is 255*8. here no sign bit needed.
assign gx=((p2-p0)+((p5-p3)<<1)+(p8-p6));//sobel mask for gradient in horiz. direction
assign gy=((p0-p6)+((p1-p7)<<1)+(p2-p8));//sobel mask for gradient in vertical direction
assign abs_gx = (gx[10]? ~gx+1 : gx); // to find the absolute value of gx.
assign abs_gy = (gy[10]? ~gy+1 : gy); // to find the absolute value of gy.
assign sum = (abs_gx+abs_gy); // finding the sum
assign out = (|sum[10:8])?8'hff : sum[7:0]; // to limit the max value to 255
endmodule
Sobel In VHDL description:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sobel is
Port(
Xnm1Ynm1 : in std_logic_vector ( 7 downto 0 );
XnYnm1 : in std_logic_vector ( 7 downto 0 );
Xnp1Ynm1 : in std_logic_vector ( 7 downto 0 );
Xnm1Yn : in std_logic_vector ( 7 downto 0 );
XnYn : in std_logic_vector ( 7 downto 0 );
Xnp1Yn : in std_logic_vector ( 7 downto 0 );
Xnm1Ynp1 : in std_logic_vector ( 7 downto 0 );
XnYnp1 : in std_logic_vector ( 7 downto 0 );
Xnp1Ynp1 : in std_logic_vector ( 7 downto 0 );
ydata_out : out std_logic_vector ( 7 downto 0 ));
end Sobel;
architecture Behavioral of Sobel is
signal op_int_vaL1 : integer;
signal op_int_vaL2 : integer;
signal op_vaL1 : integer;
signal op_vaL2 : integer;
signal abs_op_int_vaL1 : std_logic_vector (10 downto 0);
signal abs_op_int_vaL2 : std_logic_vector (10 downto 0);
signal sum : std_logic_vector (10 downto 0);
constant Xnm1Ynm1VaL1 : integer := -1;
constant XnYnm1VaL1 : integer := 0;
constant Xnp1Ynm1VaL1 : integer := 1;
constant Xnm1YnVaL1 : integer := -2;
constant XnYnVaL1 : integer := 0;
constant Xnp1YnVaL1 : integer := 2;
constant Xnm1Ynp1VaL1 : integer := -1;
constant XnYnp1VaL1 : integer := 0;
constant Xnp1Ynp1VaL1 : integer := 1;
constant Xnm1Ynm1VaL2 : integer := -1;
constant XnYnm1VaL2 : integer := -2;
constant Xnp1Ynm1VaL2 : integer := -1;
constant Xnm1YnVaL2 : integer := 0;
constant XnYnVaL2 : integer := 0;
constant Xnp1YnVaL2 : integer := 0;
constant Xnm1Ynp1VaL2 : integer := 1;
constant XnYnp1VaL2 : integer := 2;
constant Xnp1Ynp1VaL2 : integer := 1;
begin
op_int_vaL1 <= Xnm1Ynm1VaL1*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL1*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL1*CONV_INTEGER(Xnp1Ynm1)
+ Xnm1YnVaL1*CONV_INTEGER(Xnm1Yn) + XnYnVaL1*CONV_INTEGER(XnYn) + Xnp1YnVaL1*CONV_INTEGER(Xnp1Yn)
+ Xnm1Ynp1VaL1*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL1*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL1*CONV_INTEGER(Xnp1Ynp1);
op_int_vaL2 <= Xnm1Ynm1VaL2*CONV_INTEGER(Xnm1Ynm1) + XnYnm1VaL2*CONV_INTEGER(XnYnm1) + Xnp1Ynm1VaL2*CONV_INTEGER(Xnp1Ynm1)
+ Xnm1YnVaL2*CONV_INTEGER(Xnm1Yn) + XnYnVaL2*CONV_INTEGER(XnYn) + Xnp1YnVaL2*CONV_INTEGER(Xnp1Yn)
+ Xnm1Ynp1VaL2*CONV_INTEGER(Xnm1Ynp1) + XnYnp1VaL2*CONV_INTEGER(XnYnp1) + Xnp1Ynp1VaL2*CONV_INTEGER(Xnp1Ynp1);
op_vaL1 <= abs(op_int_vaL1);
op_vaL2 <= abs(op_int_vaL2);
abs_op_int_vaL1 <= CONV_std_logic_vector (op_vaL1, 11);
abs_op_int_vaL2 <= CONV_std_logic_vector (op_vaL2, 11);
sum <= abs_op_int_vaL2 + abs_op_int_vaL1;
process(sum)
if (sum > '00011111111') then
ydata_out <= "11111111";
else
ydata_out <= sum (7 downto 0);
end if;
end process;
end Behavioral;
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compile error happened in line process(sum). Thanks for your attend of reading this post.