VHDL division

[vhdl_danne]

Hi! I need to implement this in VHDL:

result=2.2*(time/timeTot-0.5)

time/timeTot is a duty cycle of a pwm signal and will always be less
than zero

Is there any simple solution for this?

Cheers! DR

 

[KJ]

Hi! I need to implement this in VHDL:

result=2.2*(time/timeTot-0.5)

time/timeTot is a duty cycle of a pwm signal and will always be less
than zero

Is there any simple solution for this?

Cheers! DR

What is the problem that you would like a simple solution for?

KJ

 

[Symon]

What is the problem that you would like a simple solution for?

KJ

He says less than zero, so maybe negative time is his problem?

Syms.

 

[KJ]

He says less than zero, so maybe negative time is his problem?

Syms.- Hide quoted text -

- Show quoted text -

Actually he said the "duty cycle of a pwm signal and will always be
less than zero"...I'm not sure I've ever run across a negative duty
cycle before, maybe they occur on perpetual motion machines or
something.

'result' would be less than zero but so what? What is the actual
problem?

KJ

 

[Mike Treseler]

I need to implement this in VHDL:
result=2.2*(time/timeTot-0.5)
time/timeTot is a duty cycle of a pwm signal and will always be less
than zero Maybe you mean less than one.
Is there any simple solution for this?

Any numeric solution for synthesis
starts with binary math.
1. Read this
http://www.emu8086.com/assembly_lan...ler_reference/numbering_systems_tutorial.html
or this
http://deadsmall.com/3J3
2. Get python
http://www.python.org/download/
3. Do the math:

Let's say we have an 8 bit pwm.
57 /evtfs/home/tres> python'0x100'
__________
Since our pwm is only 8 bits,
that '1' msb represents the counter carry out
for the FF to 00 rollover.
Now to 'fractions'.

A 25% pulse width would correspond to a count of'0x20'

A pulse, wider by a factor of 2.2
would correspond to a count of
and so it goes.

-- Mike Treseler

 

[Mike Treseler]

A 25% pulse width would correspond to a count of

12.5%

 

[beky4kr]

12.5%

I have written an article on how divide by a constant.Hope this can
help you:
----://bknpk.no-ip.biz/divide_by_constnat/divide_by_constant.html

 

[Mike Treseler]

http://bknpk.no-ip.biz/divide_by_constnat/divide_by_constant.html

Nice verilog sim example.
Thanks.

-- Mike Treseler

vlog db7.v db7_tb.v
vsim -c db7_tb -do "run -all;exit"

# Loading work.db7_tb
# Loading work.db7
# run -all
# 7 1 00000000111 00000000001 1
# 14 2 00000001110 00000000010 1
# 21 3 00000010101 00000000011 1
# 28 4 00000011100 00000000100 1
# 35 5 00000100011 00000000101 1
# 42 6 00000101010 00000000110 1
# 49 7 00000110001 00000000111 1

 

[Symon]

Nice verilog sim example.
Thanks.

-- Mike Treseler

vlog db7.v db7_tb.v
vsim -c db7_tb -do "run -all;exit"

# Loading work.db7_tb
# Loading work.db7
# run -all
# 7 1 00000000111 00000000001 1
# 14 2 00000001110 00000000010 1
# 21 3 00000010101 00000000011 1
# 28 4 00000011100 00000000100 1
# 35 5 00000100011 00000000101 1
# 42 6 00000101010 00000000110 1
# 49 7 00000110001 00000000111 1

Is it 18?

Syms.

 

[Daniel Reidal]

He says less than zero, so maybe negative time is his problem?

Syms.

Sorry to confusing you. I meant less than one...

DR

 

[Daniel Reidal]

Any numeric solution for synthesis
starts with binary math.
1. Read this
http://www.emu8086.com/assembly_lan...ler_reference/numbering_systems_tutorial.html
or this
http://deadsmall.com/3J3
2. Get python
http://www.python.org/download/
3. Do the math:

Let's say we have an 8 bit pwm.
57 /evtfs/home/tres> python
'0x100'
__________
Since our pwm is only 8 bits,
that '1' msb represents the counter carry out
for the FF to 00 rollover.
Now to 'fractions'.

A 25% pulse width would correspond to a count of
'0x20'

A pulse, wider by a factor of 2.2
would correspond to a count of
'0x46'

and so it goes.

-- Mike Treseler

Thanks. My problem is like this. I have a Current sense circuit that
will generate a PWM signal that I have to monitor. The frequency of the
pwm waveform will not be constant (because of temperature variations).
So my idea is to count BOTH pulse width and frequency of the signal to
determine the duty cycle. I'm using the formula to calculate the sense
current. My problem is I don't know how to handle decimal numbers in an
easy way. I have only used integers (signed and unsigned) in my designs.

Thanks Daniel

 

[Symon]

calculate the sense current. My problem is I don't know how to handle
decimal numbers in an easy way. I have only used integers (signed and
unsigned) in my designs.
Thanks Daniel

http://en.wikipedia.org/wiki/Binary_point
....and just in case...
http://en.wikipedia.org/wiki/Twos_complement

 

[KJ]

Thanks. My problem is like this. I have a Current sense circuit that will
generate a PWM signal that I have to monitor. The frequency of the pwm
waveform will not be constant (because of temperature variations). So my
idea is to count BOTH pulse width and frequency of the signal to determine
the duty cycle. I'm using the formula to calculate the sense current. My
problem is I don't know how to handle decimal numbers in an easy way. I
have only used integers (signed and unsigned) in my designs.

Daniel,

You're still leaving much to the imagination by not describing what you're
really after, but at least now you've added some detail. You can simply
count high time and low time of the PWM signal and you'll have all the
information you'll need about the signal, so why do you think you need to
know duty cycle?

If you have a microprocessor in your system anywhere it could easily take
the easily measurable high time and low time numbers and from that compute
the duty cycle. If not and you have an actual need for duty cycle then it
will be of the form:

DC = High time / (High time + Low time)

This 'can' be implemented in VHDL if you want, you'll likely want to scale
the numbers by some factor so that DC is in some integer range instead of 0
to 1.

Kevin Jennings

 

[Mike Treseler]

Thanks. My problem is like this. I have a Current sense circuit that
will generate a PWM signal that I have to monitor. The frequency of the
pwm waveform will not be constant (because of temperature variations).
So my idea is to count BOTH pulse width and frequency of the signal to
determine the duty cycle. I'm using the formula to calculate the sense
current.

There are two parts to any measurement.
1. Get the data.
2. Present the data.

How is this current value presented to the user?
Is he going to read it on a display or
probe the pins of your FPGA?

The simplest solution is ---|>|----/\/\/----||------
and a voltmeter.

The FPGA version of this would be to synchronize
the pwm wave to a fast clock and use it to
enable a count for a fixed time. In my world,
some Java jockey would collect these integers
and update a mA display on a web page.

My problem is I don't know how to handle decimal numbers in an
easy way. I have only used integers (signed and unsigned) in my designs.

You don't know, or you don't *want* to know?
See parts 1,2, and 3 of my previous posting.

-- Mike Treseler

 

[vhdl_danne]

Daniel,

You're still leaving much to the imagination by not describing what you're
really after, but at least now you've added some detail. You can simply
count high time and low time of the PWM signal and you'll have all the
information you'll need about the signal, so why do you think you need to
know duty cycle?

If you have a microprocessor in your system anywhere it could easily take
the easily measurable high time and low time numbers and from that compute
the duty cycle. If not and you have an actual need for duty cycle then it
will be of the form:

DC = High time / (High time + Low time)

This 'can' be implemented in VHDL if you want, you'll likely want to scale
the numbers by some factor so that DC is in some integer range instead of 0
to 1.

Kevin Jennings

Thanks. Yes, we have a microcontroller connected to the system, so we
will probably send the high and low time to it and do all calculations.
BUT, I'm just trying to find out if it is easy to do the calculations in
the FPGA.

Question:
If I have two signals of std_logic_vector, is there a way to divide them
without writing my own division routine?

I was experimenting with the code below, but as I expected the synthesis
tool (synplify, Actel, Proasic+) did not like this...

entity testDiv is
port(reset_n, clk: in std_logic;
t,ttot: in std_logic_vector(15 downto 0);
res: out std_logic_vector(31 downto 0)
);
end;

architecture rtl of testDiv is
constant i220: std_logic_vector(15 downto 0):=X"00DC";
signal temp1,temp2: integer range -32768 to 32768;
begin
process(clk, reset_n)
begin
if reset_n='0' then
res<=(others=>'0');
temp1<=0;
temp2<=0;
elsif rising_edge(clk) then
temp1<=conv_integer(i220*t);
temp2<=temp1/conv_integer(ttot)-110;
end if;
end process;
res<=conv_std_logic_vector(temp2,32);
end;

 

[KJ]

Thanks. Yes, we have a microcontroller connected to the system, so we
will probably send the high and low time to it and do all calculations.
BUT, I'm just trying to find out if it is easy to do the calculations in
the FPGA.

Question:
If I have two signals of std_logic_vector, is there a way to divide them
without writing my own division routine?

Google for lpm_divide. It takes in two std_logic_vectors and produces
the quotient and remainder.

KJ