Vhdl syntax for generate ...

Discussion in 'VHDL' started by olivier90dir, Jan 31, 2013.

  1. olivier90dir

    olivier90dir Guest

    Hi all ,

    I have a question
    I would like the equivalent of this code : A<=B(0) or B(1) or B(2) or ... B(N). with loop generate.

    I tired this code :
    CevRec: for Ilink in 0 to NB_FLT-1 generate
    A <= A or B(Ilink);
    end generate CevRec;
    result <= A ;
    remark A is an signal.
    At the compilation I have an error :
    Multiple non-tristate drivers for net ...

    Thank for yor help .

    olivier90dir, Jan 31, 2013
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  2. olivier90dir

    Rob Gaddi Guest

    On Thu, 31 Jan 2013 08:25:56 -0800 (PST)
    Can't do that with a signal, and therefore you can't do it with a
    for..generate loop. If your synthesis tool supports VHDL-2008, there's
    a unary OR operator. If not, bring in the std_logic_misc library, and
    use the OR_REDUCE function. Or you could write your own OR_REDUCE with
    a for..loop, using a variable instead of a signal, which will work. But
    either way, you want:

    result <= or B; (VHDL-2008)
    result <= OR_REDUCE(B); (earlier)
    Rob Gaddi, Jan 31, 2013
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  3. olivier90dir

    rickman Guest

    The loop should work just fine if a variable is added, then assigned to
    the signal at the end of the loop. No need for the generate statement,
    but it would need to be in a process or a function. In fact, this would
    make a good function... which is what has been done in VHDL-2008 with
    the uniary operators.

    variable temp : std_logic;

    TestCode: for Ilink in 0 to NB_FLT-1 loop
    temp := temp or B(Ilink);
    end loop;
    A <= temp;

    I've been using VHDL-2008 on my latest project and it is working well.
    My only issue is finding good documentation I can use offline. I would
    buy an e-book if I knew any given one was a good one.
    rickman, Jan 31, 2013
  4. olivier90dir

    1999outback Guest

    variable temp : std_logic;
    Don't forget to initialize the variable!
    1999outback, Jan 31, 2013
  5. olivier90dir

    rickman Guest

    Very good point. Does this do it? I'm pretty sure that unlike signals
    where initialization is not always supported in synthesis, variable
    initialization should be ok.

    variable temp : std_logic := '0';

    TestCode: for Ilink in 0 to NB_FLT-1 loop
    temp := temp or B(Ilink);
    end loop;
    A<= temp;
    rickman, Jan 31, 2013
  6. olivier90dir

    olivier90dir Guest

    Le vendredi 1 février 2013 00:44:25 UTC+1, rickman a écrit :
    Thank For your Help ...

    olivier90dir, Feb 1, 2013
  7. olivier90dir

    Andy Guest

    Synthesis supports declaration initializations in subprograms (functions orprocedures). Some FPGA synthesis tools will support declaration initializations in processes for some targets, but using them is fraught with all kinds of problems (it involves the system reset, which is best handled explicitly for a variety of reasons beyond the scope of this discussion)

    Whether it will do what you need, that depends...

    If this code is enclosed in a subprogram that is called inside a process, then the variable gets initialized each time the subprogram is called, and it will do what you need.

    However, if this code is embedded directly inside a process, the variable initialization happens only once, when the process is initialized. The process never exits, it only suspends and wakes up again, executing only the executable statements until it suspends again (declarations are not consideredexecutable statements, even if they execute a subprogram call in an initialization). Therefore, the variable is only initialized once, and will not work in this application. You would need an assignment statement prior to the loop to initialize the variable every time before the loop runs.

    Andy, Feb 4, 2013
  8. olivier90dir

    rickman Guest

    Yep, I gave the process a test and you are absolutely right, the
    variable only gets initialized once when the process is initialized.
    rickman, Feb 6, 2013
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