vhdl generate statement omit

[thedarkness]

Hello everyone,
I'm trying to create a byte comparator using single bit cascadable comparators with generate statement.

Code used:
"entity comparator_byte is
generic(n_bit:integer : = 8);
port(a,b: in bit_vector(n_bit-1 downto 0); gt,eq,lt: in bit; a_gt_b,a_eq_b,a_lt_b: out bit);
end comparator_byte;

architecture comparator_byte_ar of comparator_byte is

component bit_comp port(a,b,gt,eq,lt: in bit; a_gt_b,a_eq_b,a_lt_b: out bit); end component;

for all: bit_comp use entity work.bit_comparator(bit_comparator_ar);

signal tmp: bit_vector((n_bit-1)*3-1 downto 0);

begin

bit0: bit_comp port map(a(0),b(0),gt,eq,lt,tmp(0),tmp(1),tmp(2));

gen_stat: for i in 1 to n_bit-2 generate
begin

bit_rest: bit_comp port map(a(i),b(i),tmp(i*3-3),tmp(i*3-2),tmp(i*3-1),
tmp(i*3),tmp(i*3+1),tmp(i*3+2));

end generate gen_stat;

bit_last: bit_comp port map(a(n_bit-1),b(n_bit-1),tmp((n_bit-1)*3-3),tmp((n_bit-1)*3-2),
tmp((n_bit-1)*3-1),a_gt_b,a_eq_b,a_lt_b);

end comparator_byte_ar;"

When I try to execute it with ghdl, the elaborate session (ghdl -e) gives me this warnings:
"comparator_byte.vhdl:21:16:warning: component instance "bit_rest" is not bound
comparator_byte.vhdl:6:14:warning: (in default configuration of comparator_byte(comparator_byte_ar))"

and the code in generate statement is completely omit.
How can I resolve this problem? Thanks.

 

[joris]

Trying with ghdl... I'm not sure whether it's "correct" behavior, but it does work if you use,

component bit_comparator port(a,b,gt,eq,lt: in bit; a_gt_b,a_eq_b,a_lt_b: out bit); end component;

for all: bit_comparator use entity work.bit_comparator(bit_comparator_ar);

-- ...

bit0: bit_comparator port map(a(0),b(0),gt,eq,lt,tmp(0),tmp(1),tmp(2));

That is, using the actual name of the entity, instead of a pseudonym

 

[thedarkness]

It works!!! Thank you very much!!!!