Help using generate statement

Discussion in 'VHDL' started by koyel.aphy, Feb 12, 2014.

  1. koyel.aphy

    koyel.aphy Guest

    Hi,

    Can someone please tell me that if I declare a signal inside generate statement then whether that signal gets replicated a number of times that is dictated by the generate statement? Please take a look at the following example which is a portion of a code available online

    rounds: for i in 0 to 2 ** DEPTH - 1 generate
    signal round_k : std_logic_vector(31 downto 0);
    signal round_w : std_logic_vector(511 downto 0);
    signal round_s : std_logic_vector(255 downto 0);
    begin
    round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
    round_w <= w(i) when step = "000000" else w(i + 1);
    round_s <= s(i) when step = "000000" else s(i + 1);

    transform: sha256_transform
    port map (
    clk => clk,
    w_in => round_w,
    w_out => w(i + 1),
    s_in => round_s,
    s_out => s(i + 1),
    k => round_k
    );
    end generate;

    So do the signals round_k, round_w and round_s get replicated 2 ** DEPTH - 1 times? Also does the component sha56_transform get replicated 2 ** DEPTH - 1 times?

    Thank you,

    Best Regards
     
    koyel.aphy, Feb 12, 2014
    #1
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  2. koyel.aphy

    KJ Guest

    Yes to both questions

    Kevin Jennings
     
    KJ, Feb 12, 2014
    #2
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  3. Yes, they are.
    Yes, they are.
    Yes, that's what the generate statement is all about.

    And to be precise: the component gets instantiated 2 ** DEPTH times (so
    without "- 1").
     
    Paul Uiterlinden, Feb 12, 2014
    #3
  4. koyel.aphy

    koyel.aphy Guest

    Thank you very much for your replies. Actually round_w, round_k and round_sdo not have indices as round_w(i), round_k(i) and round_s(i) as usually the signals that are replicated under generate statements have but I think asyou said the signals will be replicated as they are declared under generate statement, they will be interpreted as round_w(i), round_k(i) and round_s(i) while implementing. Correct if I am wromg.

    Thanks again,
    Best Regards
     
    koyel.aphy, Feb 13, 2014
    #4
  5. The signals are local for each generate iteration. Just as variables are
    local to processes or subprograms, or signals declared in block statements.
    They can be declared multiple times with the same name, because they live
    in different scopes and don't see each other. The same goes for signals
    declared in a generate loop.

    How it is implemented, in don't know or care. As long as it follows the
    rules of the Language Reference Manual.

    Speaking of which, the LRM (2002 in this case) reads:

    "Elaboration of a generate statement consists of the replacement of the
    generate statement with zero or more copies of a block statement whose
    declarative part consists of the declarative items contained within the
    generate statement and whose statement part consists of the concurrent
    statements contained within the generate statement. These block statements
    are said to be represented by the generate statement. Each block statement
    is then elaborated."

    Example, also from the LRM:

    -- The following generate statement:

    LABL : for I in 1 to 2 generate
    signal s1 : INTEGER;
    begin
    s1 <= p1;
    Inst1 : and_gate port map (s1, p2(I), p3);
    end generate LABL;

    -- is equivalent to the following two block statements:

    LABL : block
    constant I : INTEGER := 1;
    signal s1 : INTEGER;
    begin
    s1 <= p1;
    Inst1 : and_gate port map (s1, p2(I), p3);
    end block LABL;

    LABL : block
    constant I : INTEGER := 2;
    signal s1 : INTEGER;
    begin
    s1 <= p1;
    Inst1 : and_gate port map (s1, p2(I), p3);
    end block LABL;

    I hope this answers your questions.

    Now that I look at the above example, I would not expect it to be allowed to
    use the same label for the two block statements...
     
    Paul Uiterlinden, Feb 13, 2014
    #5
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