M
Maurice
Hello:
I know very well VHDL, and nothing about Verilog. which is better and why?
thanks
Maurice
I know very well VHDL, and nothing about Verilog. which is better and why?
thanks
Maurice
I know very well VHDL, and nothing about Verilog. which is better and why?
Maurice said:I know very well VHDL, and nothing about Verilog. which is better and why?
Jonathan Bromley said:are you trying to incite a riot?
Mike Treseler said:Verilog has more built-in support for printing debug messages.
VHDL has more built-in support for advanced synthesis.
-- Mike Treseler
Not at all, why??
Simply, I don't know anything about verilog, I would just have an idea about
it, comparing with vhdl
Mike Treseler said:VHDL has more built-in support for advanced synthesis.
Petter said:What do you have in mind here?
Mike Treseler said:Single process entities using no signals.
Hello:
I know very well VHDL, and nothing about Verilog. which is better and why?
thanks
Maurice
Petter said:Why is single process with no signals more advanced when it comes to
synthesis?
That is certainly a matter of opinion.
Structural vs procedural.
I prefer using variables, functions, and procedures
in a single box instead of modules upon modules.
-- Mike Treseler
Mike Treseler said:That is certainly a matter of opinion.
Andy said:I also prefer the immediate update semantics of variables as opposed
to the postponed updates of signals in processes. "I stored this in
the sig up here, but it still has the old value down here later...".
David Bishop said:Verilog was written by a bunch of hardware guys who knew nothing about
software. We beat on it 'till you could do software with it.
VHDL was written by a bunch of software guys who knew nothing about
hardware. We beat on it 'till you could do hardware with it.
Petter said:I see, so it's more a matter of taste.
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