Want to understand the logic of a code

Discussion in 'VHDL' started by lkp, Jul 25, 2013.

  1. lkp

    lkp Guest

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;
    --use work.my_package.all;
    entity square_163_7_6_3 is
    port (
    a: in std_logic_vector(162 downto 0);
    z: out std_logic_vector(162 downto 0)
    );
    end square_163_7_6_3;

    architecture circuit of square_163_7_6_3 is

    signal s, t, u, s_plus_t: std_logic_vector(162 downto 0);
    signal xor1, xor2: std_logic;

    begin

    vector_s: for i in 0 to 80 generate s(2*i) <= a(i); s(2*i + 1) <= a(i+82); end generate;
    s(162) <= a(81);

    vector_t1: for j in 0 to 6 generate t(j) <= '0'; end generate;
    t(7) <= a(82);
    vector_t2: for i in 4 to 80 generate t(2*i) <= a(i+78); t(2*i + 1) <= a(i+79); end generate;
    t(162) <= a(159);

    xor1 <= a(160) xor a(161); xor2 <= a(161) xor a(162);
    u(0) <= a(160); u(1) <= a(160) xor a(162); u(2) <= a(161); u(3) <= xor1;
    u(4) <= a(82) xor a(160); u(5) <= xor2; u(6) <= a(83) xor xor1;
    u(7) <= '0'; u(8) <= a(84) xor xor1; u(9) <= '0'; u(10) <= a(85) xor xor2;
    u(11) <= '0'; u(12) <= a(86) xor a(162);
    u(13) <= '0';
    vector_u: for i in 7 to 80 generate u(2*i) <= a(i+80); u(2*i + 1) <= '0'; end generate;
    u(162) <= a(161);

    xor_gates1: for j in 0 to 162 generate s_plus_t(j) <= s(j) xor t(j); end generate;
    xor_gates2: for j in 0 to 162 generate z(j) <= s_plus_t(j) xor u(j); end generate;

    end circuit;
     
    lkp, Jul 25, 2013
    #1
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