VHDL

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comp.lang.vhdl
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IC 74374-getting incorrect simulation
  • xorro
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0
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1K
xorro
X
K
Register clear on read
  • kamalre
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0
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2K
kamalre
K
M
VHDL multiplier
  • mk7899
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0
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1K
mk7899
M
N
VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
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0
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2K
Nikos_for_vhdl
N
L
Line 50. parse error, unexpected IDENTIFIER, expecting SEMICOLON
  • Luis7910
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0
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973
Luis7910
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N
Outputting signal values to terminal Within Character Array
  • new_guy_505
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0
Views
690
new_guy_505
N
D
Binary to BCD code understanding
  • div_01
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0
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678
div_01
D
A
What does 'genbin' and 'addbins' in OSVVM mean?
  • Ash72
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0
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403
Ash72
A
R
Low level block coding
  • Roger31415
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0
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399
Roger31415
R
A
What is `transaction`event
  • Ash72
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0
Views
380
Ash72
A
R
Can anyone please help me in this code
  • ragerrani
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1
Views
468
TheAliceMay
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H
Vhdl coding
  • Harry12
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0
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356
Harry12
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H
Some Cash for Vhdl coding
  • Harry12
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0
Views
332
Harry12
H
Q
How to check time delay caused by code itself?
  • Quuruu
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1
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458
Quuruu
Q
B
Clock divide by 5
  • blesssy
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0
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390
blesssy
B
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Reed solomon decoder issue
  • lokeshvayala
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0
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310
lokeshvayala
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G
Piotrowski, Walt,
  • God1989
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0
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297
God1989
G
S
New to VHDL... Trying to convert a 2-bytes number into an decimal
  • ST3005
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0
Views
357
ST3005
S
H
VHDL: AXI-stream FIFO
  • HMSStanley
Replies
2
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868
HMSStanley
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A
How does a HEAD pointer end up pointing to the first node in a linked list?
  • Ash72
Replies
3
Views
429
Ash72
A
F
MAX6675 VHDL
  • Francovps1999
Replies
0
Views
158
Francovps1999
F
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Numeric_std.to_unsigned function in VHDL
  • ELI
Replies
0
Views
207
ELI
E

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