E
esperan
I would like to force a signal in VHDL. I know I can use TCL API in
Modelsim to do this. In fact this is exactly what I have been doing.
when -label label3 "($clk'EVENT AND $16clk = '1')" {
....
force -freeze $dummy_signal 16#[lindex $dummy_data_list 0] 0 ns,
10 ns
....
nowhen label3}
This works fine when there is only a few values that should be forced
(using several when...nowhen). But now I have a file with several
thousands of data that should be forced on to the $dummy_signal (every
clk cycle). I have tried to use one "when...nowhen" in a loop but
Modelsim just seems to get stuck and I have force the simulator to an
end.
Does someone have a solution for this problem?
Modelsim to do this. In fact this is exactly what I have been doing.
when -label label3 "($clk'EVENT AND $16clk = '1')" {
....
force -freeze $dummy_signal 16#[lindex $dummy_data_list 0] 0 ns,
10 ns
....
nowhen label3}
This works fine when there is only a few values that should be forced
(using several when...nowhen). But now I have a file with several
thousands of data that should be forced on to the $dummy_signal (every
clk cycle). I have tried to use one "when...nowhen" in a loop but
Modelsim just seems to get stuck and I have force the simulator to an
end.
Does someone have a solution for this problem?