LED Flashing

Joined
Mar 11, 2010
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Hey there.
I'm pretty new at VHDL and I've been banging my head all day long on this code but it doesn't work in any way.
The program should flash led B.

Code:
entity Flash is
	Port(
	A,B : out STD_LOGIC;
	clk: in STD_LOGIC;
	led_val: out STD_LOGIC_VECTOR(7 downto 0):="00000000");
end Flash;

architecture Behavioral of Flash is
signal clk_slow: STD_LOGIC;
signal clk_divider: STD_LOGIC_VECTOR(24 downto 0):= "0000000000000000000000000";
signal temp_val: STD_LOGIC_VECTOR(7 downto 0):="00000000";
begin
	clk_division : process(clk, clk_divider)
		begin
			if rising_edge(clk) then
				clk_divider <= clk_divider + 1;
			end if;
			clk_slow <= clk_divider(24);
		end process;
	moving : process(clk_slow,temp_val)
	begin
			if rising_edge(clk_slow) then
			temp_val <= temp_val + 1;
			end if;
         led_val<=temp_val;
	end process;
	light : process
	begin
		if temp_val(7)='1' then
		A <= '1';
		B <= '1';
		end if;
		if temp_val(7)='0' then
		B <= '0';
		end if;
	end process;
end Behavioral;

A and B are LEDS and clk is assigned to the 50 Mhz on-board oscillator.
Hope somebody can give me any tips why the code doesn't work.
Thanks in advance.
 
Joined
Mar 10, 2008
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Try this

Code:
architecture Behavioral of Flash is
signal clk_slow: STD_LOGIC;
signal clk_divider: STD_LOGIC_VECTOR(24 downto 0):= "0000000000000000000000000";
signal temp_val: STD_LOGIC_VECTOR(7 downto 0):="00000000";
begin
	clk_division : process(clk, clk_divider)
		begin
			if rising_edge(clk) then
				clk_divider <= clk_divider + 1;
			end if;
			clk_slow <= clk_divider(24);
		end process;
	moving : process(clk_slow,temp_val)
	begin
			if rising_edge(clk_slow) then
			temp_val <= temp_val + 1;
			end if;
         led_val<=temp_val;
	end process;

	light : process( temp_val)
	begin
		if temp_val(7)='1' then
		A <= '1';
		B <= '1';
		end if;
		if temp_val(7)='0' then
		B <= '0';
		end if;
	end process;
end Behavioral;
 
Joined
Mar 11, 2010
Messages
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The Synthesizer issued a warning about the missing signal in the sensitivity list but "will assume that all necessary signals are present in the sensitivity list. " Seems like my problem originated in a misassigned pin. Still, thanks for your time and your help.
 

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