most significant and less significant address

[a01lida]

i'm having a bit of problem in understand how does this work like
i'm doing a 64x4 bit static ram and it has an address of 6 bits, taking most significant 3 bits into a 3 to 8 decoder and the less significant to the 8x4 bit sram.

what i've done so far..

entity sixtyfour_by_four_sram is
	Port( add : in std_logic_vector (5 downto 0);
	        read_nwrite : in std_logic;
	        c_select : in std_logic;
	        d_inout : inout std_logic_vector (3 downto 0));
end sixtyfour_by_four_sram;

architecture Behavioral of sixtyfour_by_four_sram is

component three_to_eight_decoder
	Port ( OE : in std_logic;
	         address : in std_logic_vector (2 downto 0);
	         o_outputs : out std_logic_vector (7 downto 0));
end component;

component eight_by_four_sram 
	Port ( address : in std_logic_vector(2 downto 0);
                    read_notwrite : in std_logic;
                    chip_select : in std_logic;
                    data_inout : inout std_logic_vector(3 downto 0));
end component;

-- SIGNALS																
signal ad : std_logic_vector (2 downto 0);
signal o_put : std_logic_vector (7 downto 0);
signal d_in : std_logic_vector (3 downto 0);


begin
-- create an instance
inst : for i in 7 downto 0 generate

	gate1 : three_to_eight_decoder
	port map ( OE => c_select,
                          address => ad,
		    o_outputs => o_put);

	gate2 : eight_by_four_sram
	port map ( address => ad,
	               read_notwrite => read_nwrite,
		    chip_select => o_put(i),
		    data_inout => d_in);

end generate;

i don't think that will work
could anyone tell me how it works like (most significant and less significant) so that i can fix this?

thanks

 

[jeppe]

Hi

Your quite right - the 3 most significant bit should be used for decoding and the the rest should be used for internal addressing inside the rams

this code should work - hopefully:

entity sixtyfour_by_four_sram is
	Port( add : in std_logic_vector (5 downto 0);
			read_nwrite : in std_logic;
			c_select : in std_logic;
			d_inout : inout std_logic_vector (3 downto 0));
end sixtyfour_by_four_sram;

architecture Behavioral of sixtyfour_by_four_sram is

component three_to_eight_decoder
	Port (	OE :		in std_logic;
		address : 	in std_logic_vector (2 downto 0);
		o_outputs :         out std_logic_vector (7 downto 0));
end component;

component eight_by_four_sram 
	Port ( address : in std_logic_vector(2 downto 0);
			read_notwrite : in std_logic;
			chip_select : in std_logic;
			data_inout : inout std_logic_vector(3 downto 0));
end component;

-- SIGNALS																
--signal ad : std_logic_vector (2 downto 0);
signal o_put : std_logic_vector (7 downto 0);
signal d_in : std_logic_vector (3 downto 0);

begin

	gate1 : three_to_eight_decoder   
	port map (   	   OE => c_select,
			address => add(5 downto 3),
			o_outputs => o_put);
				  
-------------- create 8 instances of RAM
inst : for i in 7 downto 0 generate

	gate2 : eight_by_four_sram
	port map ( address => add(2 downto 0),
		  read_notwrite => read_nwrite,
			  chip_select=> o_put(i),
			  data_inout => d_in);
end generate;

end Behavioral;

Regards Jeppe

 

[a01lida]

yes it works
now i understand it
i didn't think at all to try and change the vector number!

thank you