Multiple sources ??? Example vhdl code - anyone can help ???

A

adamjoniec

Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this function.

Here is full source code:

--
Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this error.

Here is full source code:

-- file box1.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box1;

architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- file box2.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box2;

architecture box2 of box2 is
begin
PR:process(data,c)is
begin
if c='0' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;


-- file box12.vhd (ERROR ????? - HOW TO WRITE IT ANOTHER WAY ???)
library IEEE;
use IEEE.std_logic_1164.all;

entity box12 is
port (c: in STD_LOGIC;
d : out STD_LOGIC);
end box12;

architecture box12 of box12 is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

signal data1 : STD_LOGIC_VECTOR(7 downto 0);

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

end box12;


I'll we be thankfull for any help.
 
A

Andy

Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this function.

Here is full source code:

--
Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this error.

Here is full source code:

-- file box1.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box1;

architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- file box2.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box2;

architecture box2 of box2 is
begin
PR:process(data,c)is
begin
if c='0' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- file box12.vhd (ERROR ????? - HOW TO WRITE IT ANOTHER WAY ???)
library IEEE;
use IEEE.std_logic_1164.all;

entity box12 is
port (c: in STD_LOGIC;
d : out STD_LOGIC);
end box12;

architecture box12 of box12 is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

signal data1 : STD_LOGIC_VECTOR(7 downto 0);

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

end box12;

I'll we be thankfull for any help.
Click to expand...

A couple of potential sources of the problem:

Does the device you're targeting support internal tri-state buses?

If not, is there an option that needs to be selected in max+plus to
convert tri-state buses to multiplexers?

Andy
 
A

adamjoniec

A couple of potential sources of the problem:

Does the device you're targeting support internal tri-state buses?

If not, is there an option that needs to be selected in max+plus to
convert tri-state buses to multiplexers?

Andy
Click to expand...

My target device is altera epm7128s84-15 and I've noticed before that
there is a problem with tri-state buses (officially supported - but
problematic). There is no option to convert it to multiplexers.
I'm wondering if that code can be written with buffers - but I've got
no idea how to implement it.
Any idea for workaround (I want only this to work - and I don't care
about specific solution) ?
 
W

wolfgang.grafen

Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this function.

Here is full source code:

--
Hello, I'm using Max+plus and when I try to compile this code I've got
problem with multiple sources (exactly I've got error 'Signal data1
has multiple sources').
This is a little bit weird because resolved function should be
automaticly used by the compiler (at least I think so - STD_LOGIC has
got defined resolved function).
So why isn't ??? And I'm looking for any example code that will
resolve this error.

Here is full source code:

-- file box1.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box1;

architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- file box2.vhd
library IEEE;
use IEEE.std_logic_1164.all;

entity box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end entity box2;

architecture box2 of box2 is
begin
PR:process(data,c)is
begin
if c='0' then
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

-- filebox12.vhd (ERROR ????? - HOW TO WRITE IT ANOTHER WAY ???)
library IEEE;
use IEEE.std_logic_1164.all;

entitybox12is
port (c: in STD_LOGIC;
d : out STD_LOGIC);
endbox12;

architecturebox12ofbox12is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

signal data1 : STD_LOGIC_VECTOR(7 downto 0);

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

endbox12;

I'll we be thankfull for any help.
Click to expand...

Hint: you can read from an in or inout port but not from an out port.

Three possible solutions for your problem:
1. remove data from the sensitivity list in box1 and box2 and declare
data as an out port

2. declare data1 as an inout port in box12

3. rewrite your code using multiplexers if possible which is highly
preferred.

regards

Wolfgang
 
A

adamjoniec

Hint: you can read from an in or inout port but not from an out port.

Three possible solutions for your problem:
1. remove data from the sensitivity list in box1 and box2 and declare
data as an out port

2. declare data1 as an inout port in box12

3. rewrite your code using multiplexers if possible which is highly
preferred.

regards

Wolfgang
Click to expand...

ad.1. I've posted above code as an example. I've got bigger and more
complicated code and there I also read data ex.
architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
mem <= data; -- I READ HERE DATA SO IT MUST BE
INOUT PORT
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;

ad.2. I've already tried this in this code, same error

library IEEE;
use IEEE.std_logic_1164.all;

entity box12 is
port (c: in STD_LOGIC;
d : out STD_LOGIC,
data1 : inout STD_LOGIC_VECTOR(7 downto 0)); -- DATA AS
INOUT PORT, SAME ERROR
end box12;

architecture box12 of box12 is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

end box12;

ad.3. I've got no idea how to do this. I'll be gratfull for some
sample code.
 
W

wolfgang.grafen

ad.1. I've posted above code as an example. I've got bigger and more
complicated code and there I also read data ex.
architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
mem <= data; -- I READ HERE DATA SO IT MUST BE
INOUT PORT
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;
Click to expand...
A good code style would be to avoid inouts whenever possible. This in
mind I would write:
mem <= data_in when c='1' else
mem;
data <= (others => '1' when c='0' else
(others => 'Z');

which is just a way around avoiding potential errors in sensitivity
list declarations in asynchronous processes.
ad.2. I've already tried this in this code, same error
Click to expand...
I compiled it here with Modelsim without errors.
library IEEE;
use IEEE.std_logic_1164.all;

entitybox12is
port (c: in STD_LOGIC;
d : out STD_LOGIC,
data1 : inout STD_LOGIC_VECTOR(7 downto 0)); -- DATA AS
INOUT PORT, SAME ERROR
endbox12;

architecturebox12ofbox12is
component box1 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box1;
component box2 is
port(
data : inout STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC );
end component box2;

begin
box11 : box1 port map (data=>data1, c);
box22 : box2 port map (data=>data1, c);

endbox12;

ad.3. I've got no idea how to do this. I'll be gratfull for some
sample code.
Click to expand...
I assume c is not the same control signal on box1 and box2 because
either box1 or box2. Throw out c from box1 and box2 and use e.g. c1
and c2 for selecting one of the output signals from box1 and box2 or
datax in box12

begin

data12 <= data1 when c1='1' else
data2 when c2='1' else
datax;

p_box1 : box1 port map (data_in=>data12, data=>data1);
p_box2 : box2 port map (data_in=>data12, data=>data2);

regards

Wolfgang
 
W

wolfgang.grafen

ad.1. I've posted above code as an example. I've got bigger and more
complicated code and there I also read data ex.
architecture box1 of box1 is
begin
PR:process(data,c)is
begin
if c='1' then
mem <= data; -- I READ HERE DATA SO IT MUST BE
INOUT PORT
data <= "ZZZZZZZZ";
else
data <= "11111111";
end if;
end process PR;
end architecture;
Click to expand...
Just in case you only used the inout port to read back an output
signal but not an external signal you should define an intermediate
signal for data. Just write

mem <= data_i when c='1' else
mem;

data <= data_i;
data_i <= (others=>'1') when c='0' else
(others=>'Z');

and declare data as an out port.

/wolfgang
 
A

adamjoniec

Just in case you only used the inout port to read back an output
signal but not an external signal you should define an intermediate
signal for data. Just write

mem <= data_i when c='1' else
mem;

data <= data_i;
data_i <= (others=>'1') when c='0' else
(others=>'Z');

and declare data as an out port.

/wolfgang
Click to expand...

Thanks for help. It still doesn't solve my problem but anyway thank.
I'm forced to use max+plus - that's why this is a problem - a know
that this code compile with diffrent vhdl compilers.
And 'data' - is 'bus data' (in my code), I am using it to send
information beetwen processor and ram. I know that I can split one
inout port into two port (in, out) but I must do it in this way.
Is there another way to do this with inout port ?
 
A

adamjoniec

Thanks for help. It still doesn't solve my problem but anyway thank.
I'm forced to use max+plus - that's why this is a problem - a know
that this code compile with diffrent vhdl compilers.
And 'data' - is 'bus data' (in my code), I am using it to send
information beetwen processor and ram. I know that I can split one
inout port into two port (in, out) but I must do it in this way.
Is there another way to do this with inout port ?
Click to expand...

Hey, anyone ???
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Similar Threads

Multiple sources ??? Example vhdl code - anyone can help ??? 0
pls help me ; vhdl; 0
Can anyone please help me in this code 1
Illegal sequential statement (VHDL) 0
VHDL program error 2
VHDL Subtraction two’s complement 0
Help code VHDL 2
Multiplication VHDL 4

Members online

No members online now.
Total: 28 (members: 0, guests: 28)
Robots: 423

Forum statistics

Threads
473,770
Messages
2,569,584
Members
45,075
Latest member
MakersCBDBloodSupport

Latest Threads

Top