need help on VHDL


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hi
I have problem with my first program in VHDL ,
I am working with ISE 8.2
my code is:

entity mux2 is
generic(type DATA_TYPE );
port (sel : in bit; a, b : in DATA_TYPE ; z : out DATA_TYPE );
end mux2;

architecture RTL of mux2 is

begin
z <= a when sel ='0' else b;

end architecture RTL;

the problem is:
ERROR:HDLParsers:164 - "J:/FPGA/test/Mux2/mux2.vhd" Line 31. parse error, unexpected TYPE, expecting IDENTIFIER


would you please help me
 
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Help on VHDL

You do not use generic( ) for types; use a type statement like:

TYPE DATA_TYPE is std_logic_vector(15 downto 0); --use your own type
--definition

Do not use z as a port name; it will work, but it can be confusing since "Z" is a possible value of std_logic.

This should work for your entity:

entity mux2 is

port (sel : in bit; a, b : in DATA_TYPE ; z : out DATA_TYPE );

end mux2;
 
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Joined
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thanks

tooh83 said:
ISE 8.2 doesn't support generic types which is a new vhdl2008 construct

YES i think this is a cause,, i am reading from morgan kufman book,, what book do you propose to read for a fast learning?
 

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