verilog strength equivalent in vhdl

[saqman_1947]

I have a top level in vhdl (top_vhdl) that instantiates two verilog
module (a_verilog and b_verilog). I need to pass a signal from
"a_verilog"to "b_verilog" throuhg "top_vhdl". Problem is that this
signal can have any of the verilog signal strength "pull0, pull1,
weak0, weak1" while vhdl translates "pull0 and weak0" to "L" and
"pull1 and weak1" to "H".
Anyone knows how to go around it ??
Thanks

 

[Ralf Hildebrandt]

I have a top level in vhdl (top_vhdl) that instantiates two verilog
module (a_verilog and b_verilog). I need to pass a signal from
"a_verilog"to "b_verilog" throuhg "top_vhdl". Problem is that this
signal can have any of the verilog signal strength "pull0, pull1,
weak0, weak1" while vhdl translates "pull0 and weak0" to "L" and
"pull1 and weak1" to "H".
Anyone knows how to go around it ??

What about a Verilog container around that two Verilog modules?

Ralf