VHDL Beginner help

[tulio21z]

Hello friends
I'm new to vhdl and i'm having a lot of trouble.
If there is any soul kind enough to help me out i would be very gratefull.
I'm having dificulties in using nested if's. It should work since i based it on a code i found in a reference book...only that it isn't :s

The code is:

Library IEEE;
Use ieee.std_logic_1164.all;

entity TMR8BITS is
port
(
a,b,c: in std_logic_vector(7 downto 0);
s: out std_logic_vector(7 downto 0)
);
end TMR8BITS;

architecture corpo of TMR8BITS is
begin
A: PROCESS(a,b,c)
BEGIN
if ( a = b ) then
s <= a;
else if ( a = c ) then
s <= a;
else if ( b = c ) then
s <= b;
end if;
end process a;

end corpo;

--The error msg is:

Error (10500): VHDL syntax error at TMR8BITS.vhd(23) near text "process"; expecting "if"
Error (10500): VHDL syntax error at TMR8BITS.vhd(25) near text "corpo"; expecting "if"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 258 megabytes
Error: Processing ended: Sat Nov 13 22:42:23 2010
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings


Thanks is advance.

 

[jeppe]

Ok - a quick answer.

1) For each IF must there be an END IF
or
2) In your example could ELSE IF be ELSIF and this will solve the errors

Your welcome