VHDL

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comp.lang.vhdl
R
assign statement in netlist
  • rajan
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4
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10K
Kholdoun TORKI
K
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parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
  • krishlal925
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2
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joris
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about use ieee.numeric_std.all
  • lezah
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2
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Mike Treseler
M
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Re: An All Digital Phase Lock Loop
  • Ray Andraka
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13
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10K
sridevi123
S
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cannot be synthesized, bad synchronous description
  • Zenock
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7
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vipinlal
V
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DDR2 VHDL model
  • ALuPin
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8
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miheer
M
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Decimal numbers
  • Tim Hubberstey
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2
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Thomas Reinemann
T
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Port Map Array
  • Marvin.Stoltman
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3
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10K
Reiner Huober
R
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std_logic_vector signals in sensitivity list process
  • Steven Kauffmann
2
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21
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Ponceludon de Malavoy
P
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VHDL code for CIC filters
  • Sudhir
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4
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nasimnasirian
N
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Strange error in Quartus II 3.0
  • Panic
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2
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10K
Marc Guardiani
M
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free waveform drawing tool
  • Serkan
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10
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10K
timinganalyzer
T
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Using a memory initialization file
  • Walther
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8
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10K
Walther
W
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Signed Adder without overflow
  • Nemesis
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4
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10K
Nemesis
N
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problem with sll
  • Volker
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4
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10K
VHDL_HELP
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Viewing internal signals with ModelSim
  • Joseph
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4
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10K
Kevin Neilson
K
A
VHDL Behavioral and Structural Mixed Models
  • aris
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9
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10K
aris
A
N
an error on multi-source, but I can't understand...
  • Neil
Replies
11
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10K
vipinlal
V
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Rising edge of the clock
  • john
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9
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Wong
W
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Quartus II Warning: Found pins functioning as undefined clocks
  • Markus Jochim
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1
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10K
andybuonviri
A
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Signed multiplication
  • knight
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14
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10K
KJ
K
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Tightly Coupled Memories
  • kishore.ln
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2
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10K
Marcus Harnisch
M
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VHDL when question
  • Hans
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2
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10K
ALuPin
A
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Home-made SSI chips
  • JJ
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8
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10K
james
J
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Re: CAN controller VHDL code
  • hamed
Replies
5
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10K
priyankasri_1
P
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Newbie strugling with a lookup (look-up) table in VHDL (or AHDL)
  • Shannon
Replies
6
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10K
amirster
A
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Inferred latches questions
  • stoyan.shopov
Replies
3
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10K
Ralf Hildebrandt
R
D
difference between modesim XE and Modelsim SE?
  • Deville
Replies
3
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10K
David Bishop
D
E
VHDL jpeg image processing
  • eem3kc
Replies
8
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10K
bekhemali
B
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round robin arbiter
  • rt.surya
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1
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10K
Günther Jehle
G
G
About "metavalue detected, returning FALSE" warning..
  • G Iveco
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2
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10K
David Bishop
D
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Where are Huffman encoding applications?
  • Weng Tianxiang
Replies
16
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10K
Weng Tianxiang
W
B
Convert Character Variable to Integer Variable
  • Brad Smallridge
Replies
2
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10K
Brad Smallridge
B
N
ModelSim & tcl testbench
  • Niv
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2
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10K
Mike Treseler
M
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Convolution in VHDL
  • Hari
Replies
3
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10K
Guest
G
C
N-Input Gate Using Loop or Generate
  • charles.elias
Replies
7
Views
10K
kunal.bandekar
K
N
generate statement inside a process (conditional variable declaration)
  • Nicolas Matringe
Replies
5
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10K
Nicolas Matringe
N
N
Howto Create a library from vhdl source with design compiler ?
  • Nikolaos Kefalas
Replies
2
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10K
Kai Harrekilde-Petersen
K
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VHDL global signals
  • Naveen R
Replies
8
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10K
Walter Dvorak
W
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Question on Comparing two std logic vecter
  • Tha
Replies
4
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10K
eliascm
E
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Code coverage & Functional coverage tutorials
  • Raj
Replies
4
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10K
asicvlsi
A
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tool for drawing timing diagrams
  • krby_xtrm
Replies
7
Views
10K
diamondstud
D
O
Convert Between Enumeration and Integer Values
  • Olaf Petzold
Replies
4
Views
10K
Mike Treseler
M
A
How to perform a timing simulation in Modelsim with QuartusII output file ?
  • ALuPin
Replies
13
Views
9K
mouna
M
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what's the differences between the behavioral model and the RTLmodel?
  • risingsunxy
Replies
7
Views
9K
Weng Tianxiang
W
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Port mapping to (SIGNAL_NAME'range=>'0')?
  • Ken Morrow
Replies
2
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9K
Jerold Green
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PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP
  • hyeazu
Replies
9
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9K
Michael Jørgensen
M
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bit vs std_logic ?
  • Squidge
Replies
3
Views
9K
Mike Treseler
M
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What to do with "Unconnected output port" warnings?
  • Herb T
Replies
1
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9K
Stephane
S
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is function conv_std_logic_vector() synthesizable?
  • walala
Replies
2
Views
9K
Ralf Hildebrandt
R

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