Error message using Modelsim in Linux

[Ciaran]

Hello All

Thank you in advance for kindly agreeing to help me with this, as I have been stuck for quite some time.

Basically, I am receiving the following error message when using Modelsim in Linux:

** Error: (vsim-3601) Iteration limit reached at time 0 ns.

I have read previous articles relating to this particular error message and they suggest that there may be an infinite loop somewhere in my VHDL code causing Modelsim to terminate. I have scanned my code step-by-step and have made changes where I thought the problem might be but nothing has worked so far. The only thing that seems to make any difference is when I change the value of my reset signal in my test bench to '0' initially instead of '1' (See my test bench below). The simulation then runs for 10000 ns before again terminating with the same error message when reset becomes '1'. Can anyone please offer me some alternative explanation as to why this is happening? Thank you again, any suggestions are much appreciated.

Regards

Ciaran


*********************************************************
--Radix-2 Cell Array Test Bench--

library work;
library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rng_lib.all;
use work.radix2_package.all;

-----------------------------------------------------------------------------------------

entity radix2_cell_array_tb is
end radix2_cell_array_tb;

-----------------------------------------------------------------------------------------

architecture radix2_cell_array_tb of radix2_cell_array_tb is

-----------------------------------------------------------------------------------------

component radix2_cell_array
port(clk :in std_ulogic;
reset :in std_ulogic;
n :in std_ulogic_vector(width downto 0);
b :in std_ulogic_vector(width downto 0);
ain :in std_ulogic;
sum ut std_ulogic_vector(width downto 0));
end component;

-----------------------------------------------------------------------------------------

signal randomnum1 :unsigned(31 downto 0);
signal setofnums1 :std_ulogic_vector(31 downto 0);

signal randomnum2 :unsigned(31 downto 0);
signal setofnums2 :std_ulogic_vector(31 downto 0);

signal randomnum3 :unsigned(31 downto 0);
signal setofnums3 :std_ulogic_vector(31 downto 0);

signal clk :std_ulogic;
signal reset :std_ulogic;
signal n :std_ulogic_vector(width downto 0);
signal b :std_ulogic_vector(width downto 0);
signal ain :std_ulogic;
signal sum :std_ulogic_vector(width downto 0);

-----------------------------------------------------------------------------------------

begin

-----------------------------------------------------------------------------------------

radix2_cell_array_1:radix2_cell_array port map(clk,
reset,
n,
b,
ain,
sum);

-----------------------------------------------------------------------------------------

Clockrocess

begin

loop

clk <= '1';
wait for 5000 ns; --half clock cycle

clk <= '0';
wait for 5000 ns; --half clock cycle

end loop;

end process Clock;

-----------------------------------------------------------------------------------------

RSTrocess

begin

reset <= '1';
wait for 10000 ns; --clock cycle

reset <= '0';
wait;

end process RST;

-----------------------------------------------------------------------------------------

p1rocess(clk,reset)

variable r_uni1 :rand_var;
variable r_uni2 :rand_var;
variable r_uni3 :rand_var;
variable seedA1 :integer := 0;
variable seedB1 :integer := 0;
variable seedC1 :integer := 0;
variable seedA2 :integer := 0;
variable seedB2 :integer := 0;
variable seedC2 :integer := 0;
variable seedA3 :integer := 0;
variable seedB3 :integer := 0;
variable seedC3 :integer := 0;

begin

if reset = '1' then

seedA1 := seedA1 + 231; --change seed
seedB1 := seedB1 + 231; --change seed
seedC1 := seedC1 + 231; --change seed

seedA2 := seedA2 + 101; --change seed
seedB2 := seedB2 + 101; --change seed
seedC2 := seedC2 + 101; --change seed

seedA3 := seedA3 + 83; --change seed
seedB3 := seedB3 + 83; --change seed
seedC3 := seedC3 + 83; --change seed

r_uni1 := init_uniform(seedA1, seedB1, seedC1, 0.0, 100.0);
r_uni2 := init_uniform(seedA2, seedB2, seedC2, 0.0, 100.0);
r_uni3 := init_uniform(seedA3, seedB3, seedC3, 0.0, 100.0);

randomnum1 <= (others => '0');
randomnum2 <= (others => '0');
randomnum3 <= (others => '0');

elsif clk'event and clk = '1' then

r_uni1 := rand(r_uni1);
randomnum1 <= r_uni1.rnd_v;

r_uni2 := rand(r_uni2);
randomnum2 <= r_uni2.rnd_v;

r_uni3 := rand(r_uni3);
randomnum3 <= r_uni3.rnd_v;

end if;

end process p1;

-----------------------------------------------------------------------------------------

setofnums1 <= std_ulogic_vector(randomnum1);
setofnums2 <= std_ulogic_vector(randomnum2);
setofnums3 <= std_ulogic_vector(randomnum3);

ain <= setofnums1(0);
n <= setofnums2(width downto 0);
b <= setofnums3(width downto 0);

-----------------------------------------------------------------------------------------

end radix2_cell_array_tb;
*********************************************************

 

[scottcarl]

Look up this error message "Setting Simulator Control Variables With The GUI" in the Modelsim Help guide and you'll see that you need to increase your IterationLimit to a huge amount. Using DCMs(Xilinx) or PLLs(Altera) will stall at time 0 if you don't increase the iteration count. ModelSim junk that they never seem to fix.

Scottcarl