Problems compiling with ISE Webpack 8.2.01i

Discussion in 'VHDL' started by aijazbaig1, Jul 31, 2006.

  1. aijazbaig1

    aijazbaig1 Guest

    Hello Freinds.
    I am a newcomer to the field of programmable logic devices and I am
    currently trying to teach myself VHDL. I hope to learn some VHDL before
    the next semester starts.
    My sole purpose as of now is not to actually synthesise stuff but just
    to simulate the various designs that I may try to create. I am using
    the xilinx ISE webpack 8.2 on a windows XP machine.
    Below I am trying to implement a design called ones_cnt wherein the
    counter just counts the number of ones in a 4 bit array and prints the
    result in a binary format.To understand the concept of configuration
    declarations I have declared multiple architectures and I am trying to
    use the configuration declaration statement to select one the them.

    Heres my code. Its a lil big may be but I hope you guys would have a
    look.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity ones_cnt is
    Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
    C : out STD_LOGIC_VECTOR (1 downto 0));
    end ones_cnt;

    architecture Algorithmic of ones_cnt is
    begin
    process(A)
    variable NUM: INTEGER range 0 to 3;
    begin
    NUM := 0;
    for I in 0 to 2 loop
    if A(I) = '1' then
    NUM := NUM + 1;
    end if;
    end loop;
    case NUM is
    when 0 => C <= "00";
    when 1 => C <= "01";
    when 2 => C <= "10";
    when 3 => C <= "11";
    end case;
    end process;
    end Algorithmic;

    use work.all; ----- this is the line where the error is flaged!!
    ----- see below for details.
    architecture STRUCTURAL of ones_cnt is
    component MAJ3C
    port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
    end component;
    component OPAR3C
    port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
    end component;
    for all: MAJ3C use entity MAJ3(AND_OR);
    for all: OPAR3C use entity OPAR3(AND_OR);
    begin
    COMPONENT_1: MAJ3C
    port map (A,C(1));
    COMPONENT_2: OPAR3C
    port map (A,C(0));
    end STRUCTURAL;

    entity AND2 is
    port (I1,I2: in BIT; O: out BIT);
    end AND2;
    architecture BEHAVIORAL of AND2 is
    begin
    O <= I1 and I2;
    end BEHAVIORAL;

    entity OR3 is
    port (I1,I2,I3: in BIT; O: out BIT);
    end OR3;
    architecture BEHAVIORAL of OR3 is
    begin
    O <= I1 or I2 or I3;
    end BEHAVIORAL;

    use work.all;
    entity MAJ3 is
    port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
    end MAJ3;
    architecture AND_OR of MAJ3 is
    component AND2C
    port (I1,I2: in BIT; O: out BIT);
    end component;
    component OR3C
    port (I1,I2,I3: in BIT; O: out BIT);
    end component;
    for all:AND2C use entity AND2(BEHAVIOR);
    for all:OR3C use entity OR3(BEHAVIOR);
    signal A1,A2,A3: BIT;
    begin
    G1: AND2C
    port map (X(0),X(1),A1);
    G2: AND2C
    port map (X(0),X(2),A2);
    G3: AND2C
    port map (X(1),X(2),A3);
    G4: OR3C
    port map (A1,A2,A3,Z);
    end AND_OR;

    entity AND3 is
    port(I1,I2,I3: in BIT;
    O: out BIT);
    end AND3;
    architecture BEHAVIORAL of AND3 is
    begin
    O <= I1 and I2 and I3;
    end BEHAVIORAL;

    entity OR4 is
    port(I1,I2,I3,I4: in BIT;
    Z: out BIT);
    end OR4;
    architecture BEHAVIORAL of OR4 is
    begin
    Z <= X1 or X2 or X3 or X4;
    end BEHAVIORAL;

    use work.all
    entity OPAR3 is
    port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
    end OPAR3;
    architecture AND_OR of OPAR3 is
    component AND3C
    port (I1,I2,I3: in BIT; O: out BIT);
    end component;
    component OR4C
    port (I1,I2,I3,I4: in BIT; O: out BIT);
    end component;
    for all:AND3C use entity AND3(BEHAVIORAL);
    for all:OR4C use entity OR4(BEHAVIORAL);
    signal A1,A2,A3,A4: BIT;
    begin
    G1: AND3C
    port map (X(2),not X(1),not X(0),A1);
    G2: AND3C
    port map (not X(2),not X(1),X(0),A2);
    G3: AND3C
    port map (X(2),X(1),X(0),A3);
    G4: AND3C
    port map (not X(2),X(1),not X(0),A4);
    G5: OR4C
    port map (A1,A2,A3,A4,Z);
    end AND_OR;

    architecture MACRO of ones_cnt is
    begin
    C(1) <= MAJ3(A);
    C(2) <= OPAR(A);
    end MACRO;

    configuration Trial of ones_cnt is
    for STRUCTURAL
    end for;
    end Trial;

    Heres the log report generated by the compiler:
    Started : "Check Syntax".
    Running vhpcomp
    Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library
    isim_temp.
    Entity <ones_cnt> compiled.
    Entity <ones_cnt> (Architecture <algorithmic>) compiled.

    ERROR:HDLParsers:3014 - "E:/Xlinx_ISE/workbench/ones_cnt.vhd" Line 55.

    Library unit work is not available in library isim_temp.
    Parsing "AND2_stx.prj": 0.38

    Process "Check Syntax" failed


    I do not know where am I going here as my VHDL code seems to be ok but
    may be I am missing some tool-specific information here like having
    certain libraries included or something like that. I am completely new
    to this field and I would sincerely appreciate if someone guides me
    through the very difficult phase of getting started which I suppose you
    guys might have gone through too in your yesteryears. :)

    Looking forward to hearing from you,

    Best Regards,
    Aijaz.
     
    aijazbaig1, Jul 31, 2006
    #1
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  2. I'm lost... Where did all that extra code come from? Is it in your main
    file? A testbench?

    It even says that it understood what you were trying to design
    post _just_ your VHDL file. nothing more nothing less, then we;ll see what's
    going on.
    Ben
     
    Benjamin Todd, Aug 2, 2006
    #2
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  3. aijazbaig1

    Jim_B Guest

    As far as I remember Xilinx offers some documentation about recommended
    coding style. I am afraid to tell you that I recommend to read it.

    As a hint in the jungle of VHDL I would recommend to differ between VHDL
    code suited for simulation and synthesis.

    As awkward as it seems, I would strongly recommend using a clock for
    synthesiezable code.

    Hope that helps at least a bit.
     
    Jim_B, Aug 2, 2006
    #3
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