Xilinx case

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I'm an oldie (opposite of newbie, but maybe just as ignorant) who hasn't touched VHDL in over seven years. I'm using Xilinx ISE 8.2 and suddenly it won't synthesize this case statement; I swear it had and generated a RTL schematic, but maybe that was before I added the case statement.

The synthesizer reports

ERROR:Xst:739 - Failed to synthesize logic for signal <Scale0_O>.
ERROR:Xst:1431 - Failed to synthesize unit <tiny>.

but there is more help on error 739 here than there is on the Xilinx site!

Simulation runs fine, only synthesis has an issue.

Here is the code

----------------------------------------
----------------------------------------------------------------------------------
--
-- Create Date: 16:45:50 10/30/2008
-- Design Name:
-- Target Devices: XC2XL evaluation board
-- Tool versions: 8.2.031
-- Description:
--
-- Dependencies:
--
-- Revision: 1
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity tiny is
Port ( Reset_I : in STD_LOGIC;
Scale_I : in STD_LOGIC;
Clk1p8_I : in STD_LOGIC;
Scale0_O : out STD_LOGIC;
Scale1_O : out STD_LOGIC;
Scale2_O : out STD_LOGIC;
Scale3_O : out STD_LOGIC);
end tiny;


architecture Behavioral of tiny is

signal clk_scaler : unsigned(20 downto 0); -- Divides the clock and provides various divisors
signal clk : std_logic; -- Internal clock derived from oscillators
signal Scale_state : unsigned(1 downto 0); -- Scale_I state
signal Scale : std_logic; -- Scale select input debounced
signal Scale_size : unsigned(7 downto 0); -- eight bit scale multipler (255 max)
component dir_logic
port (
A : IN std_logic;
B : IN std_logic;
DIRL : OUT std_logic
);
end component;

begin

Scale <= Scale_I; -- add a debounce routine later

-- Step Scaler
process (Reset_I, Scale)
begin
if (Reset_I = '1') then
Scale_state <= (others => '0');
elsif (Scale'event) and (Scale = '1')
then
Scale_state <= Scale_state + 1; -- increment scale state
end if;
end process;

-- Scaler output
process (Reset_I, Scale_state)
begin
if (Reset_I = '1') then
Scale0_O <= '1';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00000001"; -- one is the default scale
elsif (Scale_state'event)
then
case Scale_state is
when "00" =>
Scale0_O <= '1';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00000001"; -- one
when "01" =>
Scale0_O <= '0';
Scale1_O <= '1';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00001010"; -- ten
when "10" =>
Scale0_O <= '0';
Scale1_O <= '0';
Scale2_O <= '1';
Scale3_O <= '0';
Scale_size <= "00011001"; -- twenty five
when others => -- aka "11"
Scale0_O <= '0';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '1';
Scale_size <= "00110010"; -- fifty
end case;
end if;
end process;



end Behavioral;

----------------------------------------
ah, and previewing this post, now I remember why we used to use spaces instead of tabs. Sorry!

Any help getting me back up to speed will be appreciated.

John
 
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Hi John

Well this one synthesize with a version 9.2i ISE - but with warnings
hope its useful.

your welcome
Jeppe

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity tiny is
Port ( 	Reset_I : in STD_LOGIC;
			Scale_I : in STD_LOGIC;
			Clk1p8_I : in STD_LOGIC;
			Scale0_O : out STD_LOGIC;
			Scale1_O : out STD_LOGIC;
			Scale2_O : out STD_LOGIC;
			Scale3_O : out STD_LOGIC);
end tiny;


architecture Behavioral of tiny is

	signal clk_scaler : unsigned(20 downto 0); -- Divides the clock and provides various divisors
	signal clk : std_logic; -- Internal clock derived from oscillators
	signal Scale_state : unsigned(1 downto 0); -- Scale_I state
	signal Scale : std_logic; -- Scale select input debounced
	signal Scale_size : unsigned(7 downto 0); -- eight bit scale multipler (255 max)
component dir_logic 
port (
	A : IN std_logic; 
	B : IN std_logic; 
	DIRL : OUT std_logic
);
end component; 

begin

	Scale <= Scale_I; -- add a debounce routine later
	
	-- Step Scaler
	process (Reset_I, Scale) 
	begin
		if (Reset_I = '1') then
			Scale_state <= (others => '0');
		elsif (Scale'event) and (Scale = '1') 
		then
			Scale_state <= Scale_state + 1; -- increment scale state
		end if;
	end process;

-- Scaler output
	process (Reset_I, Scale_state) 
	begin
		if (Reset_I = '1') then
			Scale0_O <= '1';
			Scale1_O <= '0';
			Scale2_O <= '0';
			Scale3_O <= '0';
			Scale_size <= "00000001"; -- one is the default scale
		else 
		case Scale_state is
		when "00" => 
			Scale0_O <= '1';
			Scale1_O <= '0';
			Scale2_O <= '0';
			Scale3_O <= '0';
			Scale_size <= "00000001"; -- one
		when "01" =>
			Scale0_O <= '0';
			Scale1_O <= '1';
			Scale2_O <= '0';
			Scale3_O <= '0';
			Scale_size <= "00001010"; -- ten
		when "10" =>
			Scale0_O <= '0';
			Scale1_O <= '0';
			Scale2_O <= '1';
			Scale3_O <= '0';
			Scale_size <= "00011001"; -- twenty five
		when others => -- aka "11"
			Scale0_O <= '0';
			Scale1_O <= '0';
			Scale2_O <= '0';
			Scale3_O <= '1';
			Scale_size <= "00110010"; -- fifty
		end case;
	end if;
end process;

end Behavioral;
 
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Thanks for checking this out Jeppe.

Hmm, now it gets interesting. I downloaded ISE release 10.1.03 - xst K.39 (nt) and I still get the same error.

Can this be something in the synthesis options (posted below)? I wouldn't think it would get device specific at this level; not until I translate and fit.

=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "GDC_top.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name : "GDC_top"
Output Format : NGC
Target Device : CoolRunner2 CPLDs

---- Source Options
Top Module Name : GDC_top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : YES
Resource Sharing : YES

---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES

---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : GDC_top.lso
Keep Hierarchy : YES
Netlist Hierarchy : as_optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Verilog 2001 : YES

---- Other Options
Clock Enable : YES
wysiwyg : NO

=========================================================================

Note that I changed the name back from 'tiny' to 'GDC_top'
 
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It looks like I found it; XST was taking a very strange way to tell me it didn't like my clocking technique. I changed my device from a coolrunner to an XC95XL and then different errors showed up. After getting rid of those errors now it works with a coolrunner.

It turns out elsif (Scale_state'event) was getting treated as a dual edge latch. Scale_state is a two bit array "xx".

My first thought is to set up a process that generates a one clock pulse when it detects a change on Scale_state, and then use the rising edge of that pulse to clock my other data. Is there a simpler way?

Why would this type of error show up in Synthesis and not later in Translation? I guess the earlier the better, but it makes it difficult to debug.
 
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Good to hear - :)

The sensitivitylist statement: process( Scale_state)
will have the same effect as Scale_state'event.

Search for the interactive book on VHDL - Evita from aldec.
chapter 6 give some nice examples about this topic

Jeppe
 
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"The sensitivitylist statement: process( Scale_state)
will have the same effect as Scale_state'event."

I've read that that only works for simulation and not synthesis. Is that old information that is no longer correct?

John
 
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Theres always a touch of black magic connected with synthesize tools ;-)
But it seems that the sensitivity statement the only option for synthesizing.

Yes the old information stil valid.

Jeppe
 

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