I'm an oldie (opposite of newbie, but maybe just as ignorant) who hasn't touched VHDL in over seven years. I'm using Xilinx ISE 8.2 and suddenly it won't synthesize this case statement; I swear it had and generated a RTL schematic, but maybe that was before I added the case statement.
The synthesizer reports
ERROR:Xst:739 - Failed to synthesize logic for signal <Scale0_O>.
ERROR:Xst:1431 - Failed to synthesize unit <tiny>.
but there is more help on error 739 here than there is on the Xilinx site!
Simulation runs fine, only synthesis has an issue.
Here is the code
----------------------------------------
----------------------------------------------------------------------------------
--
-- Create Date: 16:45:50 10/30/2008
-- Design Name:
-- Target Devices: XC2XL evaluation board
-- Tool versions: 8.2.031
-- Description:
--
-- Dependencies:
--
-- Revision: 1
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity tiny is
Port ( Reset_I : in STD_LOGIC;
Scale_I : in STD_LOGIC;
Clk1p8_I : in STD_LOGIC;
Scale0_O : out STD_LOGIC;
Scale1_O : out STD_LOGIC;
Scale2_O : out STD_LOGIC;
Scale3_O : out STD_LOGIC);
end tiny;
architecture Behavioral of tiny is
signal clk_scaler : unsigned(20 downto 0); -- Divides the clock and provides various divisors
signal clk : std_logic; -- Internal clock derived from oscillators
signal Scale_state : unsigned(1 downto 0); -- Scale_I state
signal Scale : std_logic; -- Scale select input debounced
signal Scale_size : unsigned(7 downto 0); -- eight bit scale multipler (255 max)
component dir_logic
port (
A : IN std_logic;
B : IN std_logic;
DIRL : OUT std_logic
);
end component;
begin
Scale <= Scale_I; -- add a debounce routine later
-- Step Scaler
process (Reset_I, Scale)
begin
if (Reset_I = '1') then
Scale_state <= (others => '0');
elsif (Scale'event) and (Scale = '1')
then
Scale_state <= Scale_state + 1; -- increment scale state
end if;
end process;
-- Scaler output
process (Reset_I, Scale_state)
begin
if (Reset_I = '1') then
Scale0_O <= '1';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00000001"; -- one is the default scale
elsif (Scale_state'event)
then
case Scale_state is
when "00" =>
Scale0_O <= '1';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00000001"; -- one
when "01" =>
Scale0_O <= '0';
Scale1_O <= '1';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00001010"; -- ten
when "10" =>
Scale0_O <= '0';
Scale1_O <= '0';
Scale2_O <= '1';
Scale3_O <= '0';
Scale_size <= "00011001"; -- twenty five
when others => -- aka "11"
Scale0_O <= '0';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '1';
Scale_size <= "00110010"; -- fifty
end case;
end if;
end process;
end Behavioral;
----------------------------------------
ah, and previewing this post, now I remember why we used to use spaces instead of tabs. Sorry!
Any help getting me back up to speed will be appreciated.
John
The synthesizer reports
ERROR:Xst:739 - Failed to synthesize logic for signal <Scale0_O>.
ERROR:Xst:1431 - Failed to synthesize unit <tiny>.
but there is more help on error 739 here than there is on the Xilinx site!
Simulation runs fine, only synthesis has an issue.
Here is the code
----------------------------------------
----------------------------------------------------------------------------------
--
-- Create Date: 16:45:50 10/30/2008
-- Design Name:
-- Target Devices: XC2XL evaluation board
-- Tool versions: 8.2.031
-- Description:
--
-- Dependencies:
--
-- Revision: 1
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity tiny is
Port ( Reset_I : in STD_LOGIC;
Scale_I : in STD_LOGIC;
Clk1p8_I : in STD_LOGIC;
Scale0_O : out STD_LOGIC;
Scale1_O : out STD_LOGIC;
Scale2_O : out STD_LOGIC;
Scale3_O : out STD_LOGIC);
end tiny;
architecture Behavioral of tiny is
signal clk_scaler : unsigned(20 downto 0); -- Divides the clock and provides various divisors
signal clk : std_logic; -- Internal clock derived from oscillators
signal Scale_state : unsigned(1 downto 0); -- Scale_I state
signal Scale : std_logic; -- Scale select input debounced
signal Scale_size : unsigned(7 downto 0); -- eight bit scale multipler (255 max)
component dir_logic
port (
A : IN std_logic;
B : IN std_logic;
DIRL : OUT std_logic
);
end component;
begin
Scale <= Scale_I; -- add a debounce routine later
-- Step Scaler
process (Reset_I, Scale)
begin
if (Reset_I = '1') then
Scale_state <= (others => '0');
elsif (Scale'event) and (Scale = '1')
then
Scale_state <= Scale_state + 1; -- increment scale state
end if;
end process;
-- Scaler output
process (Reset_I, Scale_state)
begin
if (Reset_I = '1') then
Scale0_O <= '1';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00000001"; -- one is the default scale
elsif (Scale_state'event)
then
case Scale_state is
when "00" =>
Scale0_O <= '1';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00000001"; -- one
when "01" =>
Scale0_O <= '0';
Scale1_O <= '1';
Scale2_O <= '0';
Scale3_O <= '0';
Scale_size <= "00001010"; -- ten
when "10" =>
Scale0_O <= '0';
Scale1_O <= '0';
Scale2_O <= '1';
Scale3_O <= '0';
Scale_size <= "00011001"; -- twenty five
when others => -- aka "11"
Scale0_O <= '0';
Scale1_O <= '0';
Scale2_O <= '0';
Scale3_O <= '1';
Scale_size <= "00110010"; -- fifty
end case;
end if;
end process;
end Behavioral;
----------------------------------------
ah, and previewing this post, now I remember why we used to use spaces instead of tabs. Sorry!
Any help getting me back up to speed will be appreciated.
John