HI :barresed:
i'm trying to do the following thing:
Signal arr: std_logic_vector(1 downto 0);
Signal BitPos: integer:=0;
process(CLK)
begin
arr(BitPos) <= Din; --Din is std_logic type
BitPos <= BitPos + 1;
end process;
I'm trying to run a TestBench in which Din is set to '0' initialy and to '1' after 10ns. Now I understand how the process works and that BitPos is actually set to 1 before Din is inserted to arr, which means Din is inserted to arr(1) insted of arr(0). All i want to do is instering the first Din into arr(0) and the second Din into arr(1).
I hope you understand my problem with the indexing, maybe you have a solution for this.
Thx,
Joe.
i'm trying to do the following thing:
Signal arr: std_logic_vector(1 downto 0);
Signal BitPos: integer:=0;
process(CLK)
begin
arr(BitPos) <= Din; --Din is std_logic type
BitPos <= BitPos + 1;
end process;
I'm trying to run a TestBench in which Din is set to '0' initialy and to '1' after 10ns. Now I understand how the process works and that BitPos is actually set to 1 before Din is inserted to arr, which means Din is inserted to arr(1) insted of arr(0). All i want to do is instering the first Din into arr(0) and the second Din into arr(1).
I hope you understand my problem with the indexing, maybe you have a solution for this.
Thx,
Joe.
Last edited: