VHDL Binary Waveform


Joined
Jul 13, 2010
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Im relatively new to VHDL, most of what I know I have been teaching myself over the last few weeks to work with an FPGA. I am programming a binary waveform in ISE except when I try to synthesize the code it comes up with an unexpected IF error.

CODE :

Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity wv4 is Port ( clk : inout STD_LOGIC);

end wv4;

begin
process (clk)
if clk = '1' then
clk <= '0' after 4 ns;

else

clk <= '1' after 4 ns;
end if;
end process;
end behavioral;

It says that there is a parse error, unexpected IF in the Underlined line. If anyone has had this problem your help would be greatly appreciated, I have been looking at it for a few days have tried different things but the same error still occurs. Thank you for your time

-Bturnbul
 
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Joined
Jul 12, 2010
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better do it this way:
Code:
    -- clock generation block

    clock : process(clk)

    begin

        clk <= not(clk) after 5 ns;

    end process clock;
 
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