VHDL

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comp.lang.vhdl
S
function read_eeprom(addr); possible?
  • steve
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3
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2K
Mike Treseler
M
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newbie question about <= and :=? what's the difference?
  • walala
Replies
3
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2K
Egbert Molenkamp
E
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(newbie) 2 read/write register
  • Max
Replies
1
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5K
eadgbe
E
M
warning?
  • Max
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2
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3K
eadgbe
E
M
array of component
  • Max
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1
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945
Ralf Hildebrandt
R
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How to get a slice of INTEGER type out?
  • walala
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1
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3K
MM
M
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switching problem
  • Simone Winkler
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5
Views
1K
William Wallace
W
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is function conv_std_logic_vector() synthesizable?
  • walala
Replies
2
Views
9K
Ralf Hildebrandt
R
J
Question: inout signal assignment
  • John Potter
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1
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3K
Renaud Pacalet
R
S
ModelSim and the Xilinix web pack unisim libraries
  • Stephen Lohning
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1
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2K
Barry Brown
B
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what are the possible reasons that successful pre-synthesis simulation + successful synthesis = fail
  • walala
Replies
4
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3K
Ralf Hildebrandt
R
V
predefined function/library
  • Vincent
Replies
3
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2K
Egbert Molenkamp
E
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SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed
  • walala
Replies
4
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2K
Technology Consultant
T
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any VHDL books on low resource(throughput, area, power trade-off) design?
  • walala
Replies
0
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1K
walala
W
K
Timing Diagram to HDL Translation
  • Kieran Francisco
Replies
9
Views
2K
VhdlCohen
V
C
Design Flow: STA to Synthesis
  • Crimson_M
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1
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2K
Brian Drummond
B
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Are all the signals read in the process should appear in the sensitivity list of the process?
  • walala
Replies
3
Views
2K
Allan Herriman
A
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Synthesizing a design with RAM.
  • Kelvin @ Singapore
Replies
0
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1K
Kelvin @ Singapore
K
K
Manipulating with the T1, T0 and TX in a SAIF file.
  • Kelvin Tsai @ Singapore
Replies
0
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1K
Kelvin Tsai @ Singapore
K
M
decoder
  • Max
Replies
2
Views
2K
Egbert Molenkamp
E
M
AWGN in VHDL
  • MACEI'S
Replies
5
Views
5K
ndrabik
N
Y
string declaration
  • Yann Sarrazin
Replies
4
Views
35K
Thomas B.
T
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what is wrong with my VHDL code? I am so dissappointed...
  • walala
Replies
3
Views
4K
Ralf Hildebrandt
R
M
again on state machine
  • Max
Replies
4
Views
2K
William Wallace
W
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FFI against VHDL for test-benches
  • Spur
Replies
4
Views
3K
Hans
H
M
R: again on state machine
  • Max
Replies
1
Views
850
William Wallace
W
L
equivalent types in different packages
  • Lolo
Replies
3
Views
1K
Lolo
L
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Silicore adopts open source business model for semiconductor IP; releases SLC1657 uP core under LGPL
  • Wade D. Peterson
Replies
0
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1K
Wade D. Peterson
W
S
Integer to slv
  • stephen henry
Replies
4
Views
2K
Mike Treseler
M
E
Tool survey for syntax for formal => actual
  • eadgbe
Replies
3
Views
1K
eadgbe
E
D
Webpack Vs. ISE
  • Dave
Replies
10
Views
5K
Nial Stewart
N
M
conversions
  • Max
Replies
0
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1K
Max
M
J
Record, Enumeration & std_logic_vector
  • Jan Kindt
Replies
5
Views
3K
Allan Herriman
A
T
Open Source Vhdl Simulators?
  • td
Replies
1
Views
7K
Tuukka Toivonen
T
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How can I infer resource re-use in my VHDL code?
  • walala
Replies
4
Views
1K
walala
W
W
where can I find good samples for efficient computation of matrix multiplication?
  • walala
Replies
2
Views
3K
joris
J
M
I cannot simulate
  • Max
Replies
1
Views
987
Jon
J
M
where to define a type?
  • Max
Replies
1
Views
827
Mike Treseler
M
W
shall I reuse a variable/signal or not?
  • walala
Replies
1
Views
921
Jon
J
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will Synposys Design Compiler support division by two's power and integer rounding?
  • walala
Replies
12
Views
3K
Jon
J
T
Is there any good book on PCI interface design?
  • tsj
Replies
4
Views
1K
Jon
J
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MODELSIM cannot display the values of a variable?
  • walala
Replies
1
Views
1K
Kai Harrekilde-Petersen
K
K
Question - aggregates..
  • Kot
Replies
4
Views
1K
Kot
K
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SOS! What can I do if Synopsys does not allow my statement?
  • walala
Replies
1
Views
1K
steve
S
C
bata takes too long with sun
  • Chuck Swart
Replies
1
Views
915
Chuck Swart
C
K
Re: When do I always put a "else NULL" statement in my VHDL code?
  • Kelvin
Replies
1
Views
6K
Kelvin
K
G
VHDL switch model
  • Grzegorz Jablonski
Replies
0
Views
11K
Grzegorz Jablonski
G
V
compilation error with ModelSim
  • Vincent
Replies
3
Views
2K
Jon
J
J
DDC design
  • Jan
Replies
2
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2K
Ray Andraka
R
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NEWBIE ASKING FOR HELP! can anybody take a look at my Synopsys DC report?
  • walala
Replies
2
Views
2K
walala
W

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