VHDL

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comp.lang.vhdl
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Cannot find function "TO_INTEGER" for these actuals
  • Travis
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16
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2K
Andy
A
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Distributed Ram with Initial Values (Virtex)
  • Travis
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11
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1K
Andy
A
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How can I avoid variable in this loop (outside the process)?
  • troll greenЪ
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5
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764
Paul Uiterlinden
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signal ram: ram_t := (others => (others '0'));
  • Travis
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3
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2K
Andy
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Signal xx cannot be synthesized, bad synchronous description error
  • robbevt
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15
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3K
robbevt
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Chasing Bugs in the Fog
  • rickman
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3
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1K
Nicolas Matringe
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vmkr segmentation fault
  • alb
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1
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842
Paul Uiterlinden
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[ANN] LOOPGEN-Fast hardware looping VHDL IPs
  • Nikolaos Kavvadias
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0
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1K
Nikolaos Kavvadias
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E
DSP48 in synchronous process or not, what's the difference?
  • Ethan Zheng
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2
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792
goouse99
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X
2 bit multiplier
  • xiibweb
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6
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24K
sergio
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N
A few question about vhdl(clk,signal,etc..)
  • natiben27
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3
Views
908
Andy
A
B
2 counters, counting states of Bit stream
  • brandon.spiteri
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16
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2K
Andy
A
D
ram problem
  • dwi jayanto Wibowo
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2
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920
Andy
A
B
Synchronous programmable counter
  • Brandon Spiteri
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1
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2K
Nicolas Matringe
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How do measure Power,Delay and area in vhdl
  • Noura
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0
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864
Noura
N
A
HELP! VHDL real TYPE produces infinite decimal. How to approximateor reduce precision?
  • adam.kimura
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3
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1K
adam.kimura
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Cascading the attributes
  • valtih1978
Replies
5
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736
Andy
A
I
get accustomed with vhdl 2008
  • Ishaan Wadhwa
Replies
2
Views
894
valtih1978
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C
Calculating Pulse per minute in a FPGA
  • Cory Shol
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6
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1K
chrisabele
C
S
train ticket machine help needed!
  • sicazoR
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0
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1K
sicazoR
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implementation of traffic light...
  • danddad61
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5
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1K
rickman
R
I
abstract type signal
  • Ilya Kalistru
Replies
3
Views
785
kevin.neilson
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A
clocked process and sensitivity list
  • alb
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19
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2K
Andy
A
J
VHDL Standards Invitation and Status
  • Jim Lewis
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3
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1K
Jim Lewis
J
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Displaying a 4-digit integer number on 7-segments
  • tudorc11
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0
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2K
tudorc11
T
B
Counting number of asserted register bits in VHDL
  • bucketonuts
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12
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2K
Andy
A
C
Asynchronous With Select and When Else Statements
  • Cory Shol
Replies
6
Views
1K
rickman
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R
Generics, packages, and VHDL-2008
  • Rob Gaddi
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5
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1K
Rob Gaddi
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i need solutions of chapter 5 wireless communication by AndreaGoldsmith
  • tahir
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2
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3K
mrdungdoan
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C
VHDL mod operator
  • cbr_929rr
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5
Views
76K
Mehdi1149
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VHDL Model for a MIPS Processor
  • jdavis7667
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1
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1K
Andy
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Design entry poll: which is your favorite editor?
  • Philippe
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1
Views
770
alb
A
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VHDL code PROBLEM ,how to create shift left operation withoutregister in vhdl
  • Wing Chun
Replies
7
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3K
Andy
A
V
write(output, string)
  • valtih1978
Replies
0
Views
784
valtih1978
V
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conv_integer
  • geeta k
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1
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1K
[email protected]
R
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Compiling error... not sure how to address the errors
  • Zak Asaad
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5
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1K
Zak Asaad
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CFP - High-level synthesis - Methodologies and Practice
  • Nikolaos Kavvadias
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0
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1K
Nikolaos Kavvadias
N
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Convert ADC output format to DAC input
  • snake368
Replies
7
Views
1K
Andy
A
A
configurable number of interfaces
  • ananth kamath
Replies
5
Views
845
ananth kamath
A
C
Dual Edged Counter
  • Cory Shol
Replies
6
Views
1K
rickman
R
S
need vhdl code for 8 bit simple cpu
  • say
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0
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1K
say
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Hexadecimal value (literal) as function parameter, is it possible?
  • wimille
Replies
3
Views
1K
Andy
A
A
Definition Multiply and Division in VHDL
  • Adnan86
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0
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2K
Adnan86
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mutliple input through same input lines
  • paviinelec
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0
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829
paviinelec
P
B
Architecture name through hierarchy
  • blaise.mulliez
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6
Views
994
KJ
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Which function takes precedence when multiple are visible?
  • kevin.neilson
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1
Views
839
KJ
K
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"Non-static aggregate with multiple choices has non-static otherschoice."
  • rickman
Replies
5
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1K
rickman
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Error which Don't know how to solve... newbie
  • pplnet
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2
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5K
marina_yassa
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image compression using golomb-rice algorithm
  • gokuldeep
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0
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2K
gokuldeep
G
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precedence of a downto clause
  • ejubenville
Replies
0
Views
859
ejubenville
E

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